diff options
| author | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:39:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:39:09 +0200 |
| commit | ef286d8f3e02f7ef5b227f28e66b05122d816129 (patch) | |
| tree | 0c8a6079e0fbe0fa80c7a21e09b0ff58a5165378 /library/wrapper/bram.v | |
| parent | 31e54157acbceca921733da0a9fc521398f06e1b (diff) | |
| download | ghdl-yosys-plugin-ef286d8f3e02f7ef5b227f28e66b05122d816129.tar.gz ghdl-yosys-plugin-ef286d8f3e02f7ef5b227f28e66b05122d816129.tar.bz2 ghdl-yosys-plugin-ef286d8f3e02f7ef5b227f28e66b05122d816129.zip | |
Adjust ecp5_versa tests. Wrappers for verilog modules are not needed anymore.
Diffstat (limited to 'library/wrapper/bram.v')
| -rw-r--r-- | library/wrapper/bram.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/library/wrapper/bram.v b/library/wrapper/bram.v index 03859dc..cd99939 100644 --- a/library/wrapper/bram.v +++ b/library/wrapper/bram.v @@ -1,7 +1,7 @@ // Workaround BRAM implementation for fifo buffer // 2020 <hackfin@section5.ch> -module bram_2psync_6_8_59fe624214af9b8daa183282288d5eb56b321f14 #( +module bram_2psync #( parameter DATA = 8, parameter ADDR = 6 ) ( |