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| author | Anton Blanchard <anton@linux.ibm.com> | 2019-11-04 04:48:29 +1100 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-11-03 18:48:29 +0100 |
| commit | 3cefdbec000eb69d27070c6ecfa87e109219df95 (patch) | |
| tree | ccefd8553b719777e5b79f41c94dd156712a86d3 /src | |
| parent | 0ac58d2a569dae3db5d53c70750c5cb0b535ce8b (diff) | |
| download | ghdl-yosys-plugin-3cefdbec000eb69d27070c6ecfa87e109219df95.tar.gz ghdl-yosys-plugin-3cefdbec000eb69d27070c6ecfa87e109219df95.tar.bz2 ghdl-yosys-plugin-3cefdbec000eb69d27070c6ecfa87e109219df95.zip | |
Add Id_Smod support (#66)
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index d2d33e6..814f613 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -512,6 +512,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Asr: case Id_Smul: case Id_Umul: + case Id_Smod: case Id_Allconst: case Id_Allseq: case Id_Anyconst: @@ -672,6 +673,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Umul: module->addMul(to_str(iname), IN(0), IN(1), OUT(0), false); break; + case Id_Smod: + module->addMod(to_str(iname), IN(0), IN(1), OUT(0), true); + break; case Id_Mux2: module->addMux(to_str(iname), IN(1), IN(2), IN(0), OUT(0)); break; |