diff options
| -rw-r--r-- | src/ghdl.cc | 4 | ||||
| -rwxr-xr-x | testsuite/pr66/testsuite.sh | 9 | ||||
| -rw-r--r-- | testsuite/pr66/vector.vhdl | 14 |
3 files changed, 27 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index d2d33e6..814f613 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -512,6 +512,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Asr: case Id_Smul: case Id_Umul: + case Id_Smod: case Id_Allconst: case Id_Allseq: case Id_Anyconst: @@ -672,6 +673,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Umul: module->addMul(to_str(iname), IN(0), IN(1), OUT(0), false); break; + case Id_Smod: + module->addMod(to_str(iname), IN(0), IN(1), OUT(0), true); + break; case Id_Mux2: module->addMux(to_str(iname), IN(1), IN(2), IN(0), OUT(0)); break; diff --git a/testsuite/pr66/testsuite.sh b/testsuite/pr66/testsuite.sh new file mode 100755 index 0000000..114c9d7 --- /dev/null +++ b/testsuite/pr66/testsuite.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +. ../testenv.sh + +run_yosys -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il" + +grep -q 'connect \\v 63' vector.il || exit 1 + +clean diff --git a/testsuite/pr66/vector.vhdl b/testsuite/pr66/vector.vhdl new file mode 100644 index 0000000..3eb9951 --- /dev/null +++ b/testsuite/pr66/vector.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector is + port (v: out integer + ); +end vector; + +architecture synth of vector is + +begin + v <= to_integer(unsigned'(x"7fffffff")) mod 64; +end synth; |