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| author | T. Meissner <programming@goodcleanfun.de> | 2019-10-09 18:33:15 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-10-09 18:33:15 +0200 |
| commit | 9a8c8162b869479017ccb6f642fadce717685fa3 (patch) | |
| tree | 2aab226121736fd0c8f900be4c5359d26fdf2b29 /src | |
| parent | b405a27654f326eb1117c0eda8e7389a64fc5c94 (diff) | |
| download | ghdl-yosys-plugin-9a8c8162b869479017ccb6f642fadce717685fa3.tar.gz ghdl-yosys-plugin-9a8c8162b869479017ccb6f642fadce717685fa3.tar.bz2 ghdl-yosys-plugin-9a8c8162b869479017ccb6f642fadce717685fa3.zip | |
Handle Id_Sextend (#59)
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 58c738e..83b76d0 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -75,6 +75,12 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) res.extend_u0(get_width(n), false); return res; } + case Id_Sextend: + { + RTLIL::SigSpec res = IN(0); + res.extend_u0(get_width(n), true); + return res; + } case Id_Utrunc: case Id_Strunc: { @@ -325,6 +331,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Const_Z: case Id_Const_X: case Id_Uextend: + case Id_Sextend: case Id_Utrunc: case Id_Strunc: case Id_Extract: @@ -510,6 +517,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Const_Z: case Id_Const_X: case Id_Uextend: + case Id_Sextend: case Id_Utrunc: case Id_Strunc: case Id_Extract: |