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| author | Tristan Gingold <tgingold@free.fr> | 2020-11-18 21:48:30 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-11-18 21:48:30 +0100 |
| commit | 8265c87d82b2cba1ea196cf847dedecbaa77d27d (patch) | |
| tree | bb9e22cba878aafb0d7bf5ed541f789ee0f7fbb8 /testsuite/examples/blackbox/blackbox3.vhdl | |
| parent | e43666c176544ba8bac0d1b89b6ac8e19abd2c28 (diff) | |
| download | ghdl-yosys-plugin-8265c87d82b2cba1ea196cf847dedecbaa77d27d.tar.gz ghdl-yosys-plugin-8265c87d82b2cba1ea196cf847dedecbaa77d27d.tar.bz2 ghdl-yosys-plugin-8265c87d82b2cba1ea196cf847dedecbaa77d27d.zip | |
example/blackbox: tune the test for previous commit
Diffstat (limited to 'testsuite/examples/blackbox/blackbox3.vhdl')
| -rw-r--r-- | testsuite/examples/blackbox/blackbox3.vhdl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/testsuite/examples/blackbox/blackbox3.vhdl b/testsuite/examples/blackbox/blackbox3.vhdl index a506df0..864247d 100644 --- a/testsuite/examples/blackbox/blackbox3.vhdl +++ b/testsuite/examples/blackbox/blackbox3.vhdl @@ -9,10 +9,10 @@ end; architecture behav of blackbox3 is component \lib__cell__box2.3\ is port (a, b : std_logic; - \OUT\ : out std_logic); + \O\ : out std_logic); end component; begin inst: \lib__cell__box2.3\ - port map (a => a, b => b, \OUT\ => o); + port map (a => a, b => b, \O\ => o); end behav; |