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authorTristan Gingold <tgingold@free.fr>2021-10-02 19:21:00 +0200
committerTristan Gingold <tgingold@free.fr>2021-10-02 19:21:21 +0200
commitd6a6572439a1f3d7d8c55ae181b978d693ab85d2 (patch)
tree6aaebdf0043acab8768145d87a1347247c90f205 /testsuite/issues/issue158/repro3.vhdl
parenta0b84cc52e26bfaf35a947a8e7e76b576b4d92c0 (diff)
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testsuite: add a test for #158
Diffstat (limited to 'testsuite/issues/issue158/repro3.vhdl')
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diff --git a/testsuite/issues/issue158/repro3.vhdl b/testsuite/issues/issue158/repro3.vhdl
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+++ b/testsuite/issues/issue158/repro3.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro3 is
+ port(
+ clk : in std_logic;
+ inp : std_logic;
+ module_to_clk_cross : out std_ulogic);
+end;
+
+architecture arch of repro3 is
+ type variables_t is record
+ iftrue : std_logic_vector(3 downto 0);
+ inp : std_logic;
+ return_output : std_logic_vector(3 downto 0);
+ end record;
+begin
+ process (clk) is
+ variable read_pipe : variables_t;
+ variable write_pipe : variables_t;
+ begin
+ write_pipe := read_pipe;
+ write_pipe.inp := inp;
+ read_pipe := write_pipe;
+ end process;
+end arch;