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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-06 03:55:50 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-06 03:55:50 +0100 |
| commit | 690470aa7380ce198bfa170977a0932b83123a72 (patch) | |
| tree | 2b5b0e29ee39d99e102216dd2b3f7a9262199e4e /testsuite/issues/issue7/testsuite.sh | |
| parent | 4d1d02bc7e777a39122fdeefaa4559615c1d106d (diff) | |
| download | ghdl-yosys-plugin-690470aa7380ce198bfa170977a0932b83123a72.tar.gz ghdl-yosys-plugin-690470aa7380ce198bfa170977a0932b83123a72.tar.bz2 ghdl-yosys-plugin-690470aa7380ce198bfa170977a0932b83123a72.zip | |
testsuite: reduce verbosity.
Diffstat (limited to 'testsuite/issues/issue7/testsuite.sh')
| -rwxr-xr-x | testsuite/issues/issue7/testsuite.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/issues/issue7/testsuite.sh b/testsuite/issues/issue7/testsuite.sh index 5d396dc..2ca1ccb 100755 --- a/testsuite/issues/issue7/testsuite.sh +++ b/testsuite/issues/issue7/testsuite.sh @@ -6,7 +6,7 @@ topdir=../.. run_yosys -Q -q -p "ghdl ref.vhdl -e vector ref; write_verilog ref.v" run_yosys -Q -q -p "ghdl ref.vhdl vector.vhdl -e vector synth; write_verilog vector.v" -run_yosys -Q -p ' +run_yosys -q -p ' read_verilog ref.v rename vector ref |