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author | Tristan Gingold <tgingold@free.fr> | 2020-03-29 20:25:54 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-29 20:26:11 +0200 |
commit | 6625c5c1b2d7188546e1f34449f87adaa58e9699 (patch) | |
tree | bb2f58b4037c249531b5c61a8f26b03899cc5929 /testsuite/issues/issue96/ent.vhdl | |
parent | f37374f1b2eee45243e3b4a58082f83319af053c (diff) | |
download | ghdl-yosys-plugin-6625c5c1b2d7188546e1f34449f87adaa58e9699.tar.gz ghdl-yosys-plugin-6625c5c1b2d7188546e1f34449f87adaa58e9699.tar.bz2 ghdl-yosys-plugin-6625c5c1b2d7188546e1f34449f87adaa58e9699.zip |
Add a test for #96
Diffstat (limited to 'testsuite/issues/issue96/ent.vhdl')
-rw-r--r-- | testsuite/issues/issue96/ent.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/issues/issue96/ent.vhdl b/testsuite/issues/issue96/ent.vhdl new file mode 100644 index 0000000..8f2f1b5 --- /dev/null +++ b/testsuite/issues/issue96/ent.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + a : inout std_logic; + enable : in std_logic; + d_in : in std_logic; + d_out : out std_logic + ); +end; + +architecture a of ent is +begin + process(all) + begin + if enable then + a <= d_in; + else + a <= 'Z'; + end if; + end process; + d_out <= a; +end; |