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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-07 08:18:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-07 08:18:47 +0200 |
| commit | ad7cd6279cccb149644ef124b3d46867afa66162 (patch) | |
| tree | 245761c50f1dcc7a665a8e1252679667b38fca46 /testsuite/issues/pr61/vector.vhdl | |
| parent | f2dd8b7a569fb1705e5d5113b75bb5a28006feec (diff) | |
| download | ghdl-yosys-plugin-ad7cd6279cccb149644ef124b3d46867afa66162.tar.gz ghdl-yosys-plugin-ad7cd6279cccb149644ef124b3d46867afa66162.tar.bz2 ghdl-yosys-plugin-ad7cd6279cccb149644ef124b3d46867afa66162.zip | |
Adjust test with incorrect value.
Diffstat (limited to 'testsuite/issues/pr61/vector.vhdl')
| -rw-r--r-- | testsuite/issues/pr61/vector.vhdl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/issues/pr61/vector.vhdl b/testsuite/issues/pr61/vector.vhdl index ea83bc2..4c0f4c9 100644 --- a/testsuite/issues/pr61/vector.vhdl +++ b/testsuite/issues/pr61/vector.vhdl @@ -15,5 +15,5 @@ begin v1 <= x"0ffffffffffffff0"; v <= v1+(-1); u1 <= x"00ffffffffffff00"; - u <= u1 +4294967290; + u <= u1 + (-6); -- +4294967290; end synth; |