blob: 4c0f4c98f5aaafa520b1e192526f397c2c1554f1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vector is
port (v: out signed(63 downto 0);
u: out unsigned(63 downto 0));
end vector;
architecture synth of vector is
signal v1 : signed (63 downto 0);
signal u1 : unsigned (63 downto 0);
begin
v1 <= x"0ffffffffffffff0";
v <= v1+(-1);
u1 <= x"00ffffffffffff00";
u <= u1 + (-6); -- +4294967290;
end synth;
|
