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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-09 18:18:57 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-09 18:18:57 +0100 |
| commit | 0ccb67f997d2243ef2268811ace3af045fa5481e (patch) | |
| tree | d49cff67560b4a8882296051e344037d425fc094 /testsuite/issues | |
| parent | 71c4894dbf62645eaaab0e0b6d9f1d893577a3c8 (diff) | |
| download | ghdl-yosys-plugin-0ccb67f997d2243ef2268811ace3af045fa5481e.tar.gz ghdl-yosys-plugin-0ccb67f997d2243ef2268811ace3af045fa5481e.tar.bz2 ghdl-yosys-plugin-0ccb67f997d2243ef2268811ace3af045fa5481e.zip | |
Add test for previous commit.
Diffstat (limited to 'testsuite/issues')
| -rw-r--r-- | testsuite/issues/bug-loop1/loop1.vhdl | 14 | ||||
| -rwxr-xr-x | testsuite/issues/bug-loop1/testsuite.sh | 11 |
2 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/issues/bug-loop1/loop1.vhdl b/testsuite/issues/bug-loop1/loop1.vhdl new file mode 100644 index 0000000..9d512b0 --- /dev/null +++ b/testsuite/issues/bug-loop1/loop1.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity loop1 is + port (a : std_logic_vector (7 downto 0); + o : out std_logic_vector (15 downto 0)); +end; + +architecture behav of loop1 is + signal s : std_logic_vector (15 downto 0); +begin + s <= a & s (15 downto 8); + o <= s; +end behav; diff --git a/testsuite/issues/bug-loop1/testsuite.sh b/testsuite/issues/bug-loop1/testsuite.sh new file mode 100755 index 0000000..3ec2ece --- /dev/null +++ b/testsuite/issues/bug-loop1/testsuite.sh @@ -0,0 +1,11 @@ +#!/bin/sh + +topdir=../.. +. $topdir/testenv.sh + +for f in loop1; do + synth "${f}.vhdl -e ${f}" +done + +clean +echo OK |