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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:39:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:39:09 +0200 |
| commit | ef286d8f3e02f7ef5b227f28e66b05122d816129 (patch) | |
| tree | 0c8a6079e0fbe0fa80c7a21e09b0ff58a5165378 /testsuite | |
| parent | 31e54157acbceca921733da0a9fc521398f06e1b (diff) | |
| download | ghdl-yosys-plugin-ef286d8f3e02f7ef5b227f28e66b05122d816129.tar.gz ghdl-yosys-plugin-ef286d8f3e02f7ef5b227f28e66b05122d816129.tar.bz2 ghdl-yosys-plugin-ef286d8f3e02f7ef5b227f28e66b05122d816129.zip | |
Adjust ecp5_versa tests. Wrappers for verilog modules are not needed anymore.
Diffstat (limited to 'testsuite')
| -rwxr-xr-x | testsuite/examples/test-ecp5_versa/testsuite.sh | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/testsuite/examples/test-ecp5_versa/testsuite.sh b/testsuite/examples/test-ecp5_versa/testsuite.sh index 44dac88..8574b94 100755 --- a/testsuite/examples/test-ecp5_versa/testsuite.sh +++ b/testsuite/examples/test-ecp5_versa/testsuite.sh @@ -16,7 +16,6 @@ VHDL_SYN_FILES="$src/versa_ecp5_top.vhdl \ VERILOG_FILES="\ $top/library/wrapper/primitives.v \ - $top/library/wrapper/wrapper.v \ $top/library/wrapper/bram.v " |