1 files changed, 15 insertions, 0 deletions
diff --git a/testsuite/pr61/vector.vhdl b/testsuite/pr61/vector.vhdl
new file mode 100644
index 0000000..61a0d67
--- /dev/null
+++ b/testsuite/pr61/vector.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+  port (v: out signed(63 downto 0);
+        u: out unsigned(63 downto 0));
+end vector;
+
+architecture synth of vector is
+
+begin
+  v <= signed'(x"0ffffffffffffff0")+(-1);
+  u <= unsigned'(x"00ffffffffffff00")+4294967290;
+end synth;