1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/pr66/vector.vhdl b/testsuite/pr66/vector.vhdl
new file mode 100644
index 0000000..3eb9951
--- /dev/null
+++ b/testsuite/pr66/vector.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+    port (v: out integer
+          );
+end vector;
+
+architecture synth of vector is
+
+begin
+    v <= to_integer(unsigned'(x"7fffffff")) mod 64;
+end synth;