6 files changed, 77 insertions, 0 deletions

diff --git a/testsuite/issues/issue11/test_nand.vhdl b/testsuite/issues/issue11/test_nand.vhdl
new file mode 100644
index 0000000..ae60966
--- /dev/null
+++ b/testsuite/issues/issue11/test_nand.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_nand is port (
+    sel0, sel1: in std_logic;
+    c: out std_logic);
+end test_nand;
+
+architecture synth of test_nand is
+begin
+
+    c <= sel1 nand sel0;
+
+end synth;
diff --git a/testsuite/issues/issue11/test_nor.vhdl b/testsuite/issues/issue11/test_nor.vhdl
new file mode 100644
index 0000000..f5f911e
--- /dev/null
+++ b/testsuite/issues/issue11/test_nor.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_nor is port (
+    sel0, sel1: in std_logic;
+    c: out std_logic);
+end test_nor;
+
+architecture synth of test_nor is
+begin
+
+    c <= sel1 nor sel0;
+
+end synth;
diff --git a/testsuite/issues/issue11/test_or.vhdl b/testsuite/issues/issue11/test_or.vhdl
new file mode 100644
index 0000000..d39d064
--- /dev/null
+++ b/testsuite/issues/issue11/test_or.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_or is port (
+    sel0, sel1: in std_logic;
+    c: out std_logic);
+end test_or;
+
+architecture synth of test_or is
+begin
+
+    c <= sel1 or sel0;
+
+end synth;
diff --git a/testsuite/issues/issue11/test_xnor.vhdl b/testsuite/issues/issue11/test_xnor.vhdl
new file mode 100644
index 0000000..4a706f0
--- /dev/null
+++ b/testsuite/issues/issue11/test_xnor.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_xnor is port (
+    sel0, sel1: in std_logic;
+    c: out std_logic);
+end test_xnor;
+
+architecture synth of test_xnor is
+begin
+
+    c <= sel1 xnor sel0;
+
+end synth;
diff --git a/testsuite/issues/issue11/test_xor.vhdl b/testsuite/issues/issue11/test_xor.vhdl
new file mode 100644
index 0000000..b856745
--- /dev/null
+++ b/testsuite/issues/issue11/test_xor.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_xor is port (
+    sel0, sel1: in std_logic;
+    c: out std_logic);
+end test_xor;
+
+architecture synth of test_xor is
+begin
+
+    c <= sel1 xor sel0;
+
+end synth;
diff --git a/testsuite/issues/issue11/testsuite.sh b/testsuite/issues/issue11/testsuite.sh
new file mode 100755
index 0000000..7aecfc9
--- /dev/null
+++ b/testsuite/issues/issue11/testsuite.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+for f in or xor nor nand xnor; do
+  synth "test_${f}.vhdl -e test_${f}"
+done
+
+clean