test_nor.vhdl « issue11 « issues « testsuite - iCE40/ghdl-yosys-plugin

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library ieee;
use ieee.std_logic_1164.all;

entity test_nor is port (
    sel0, sel1: in std_logic;
    c: out std_logic);
end test_nor;

architecture synth of test_nor is
begin

    c <= sel1 nor sel0;

end synth;