aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Move formal tests for gates into single subdirectoryXiretza2020-03-2210-10/+1
|
* Add abs gate (#91)Xiretza2020-03-105-0/+69
|
* Fix ghdl.cc indentation (#90)Xiretza2020-03-101-168/+169
| | | | Switched everything to tabs, since those seemed to be most common. Also added a vim modeline.
* Add test for previous commit.Tristan Gingold2020-03-092-0/+25
|
* ghdl.cc: avoid infinite recursion due to concatenation.Tristan Gingold2020-03-091-2/+50
|
* ghdl.cc: refactoring before optimization.Tristan Gingold2020-03-091-25/+26
|
* ghdl.cc: rewrite help.Tristan Gingold2020-03-011-2/+23
|
* Show usage with nextpnr instead of arachne-pnr in README (#88)Xiretza2020-02-231-4/+6
|
* ghdl.cc: adjust after changes in ghdl (for memories).Tristan Gingold2020-02-231-4/+16
|
* Add a test for issue 1107Tristan Gingold2020-02-152-0/+24
|
* Added ECP5 example for Lattice versa devkit (#85)Martin2020-02-1429-0/+6692
| | | | | | | - LED blinky - Added support for vendor primitives - Workarounds in Verilog for BRAM and primitive wrapping - Docker support Makefiles - openocd support files
* ci: use image with pre-built GHDL (#81)eine2020-01-212-55/+25
| | | | | | * ci: use image with pre-built GHDL * ci: execute 'push' workflow on pull_request too
* Make test logs mode consistent: Add OK status. For #79Tristan Gingold2020-01-206-0/+6
|
* migrate from Travis to GHA and rework examples (#78)eine2020-01-1953-439/+174
| | | | | | * migrate from Travis to GHA * rework examples
* add cons_0, div, and umod (#72)Pepijn de Vos2019-12-311-2/+22
| | | | | | * add cons_0, [su]div, and umod * Yosys mod is actually remainder semantics
* testsuite: add reproducer for #76Tristan Gingold2019-12-312-0/+38
|
* Add more tests for issue#36Tristan Gingold2019-12-053-0/+71
|
* Add testcase for #73Tristan Gingold2019-12-054-0/+63
|
* handle mem_rd_sync gates.Tristan Gingold2019-12-051-0/+10
|
* Handle removal of id_output gates.Tristan Gingold2019-12-051-28/+10
|
* Fix init input for iadff. For #76Tristan Gingold2019-12-031-1/+1
|
* Add test for #75Tristan Gingold2019-12-032-0/+55
|
* Do not rename ports. Fix #75Tristan Gingold2019-12-031-8/+9
|
* Support multiple synthesis. Fix #73Tristan Gingold2019-12-021-4/+7
|
* Adjust pr61 testcase to avoid constant propagation.Tristan Gingold2019-11-161-2/+6
|
* Add testcase from #36Tristan Gingold2019-11-072-0/+42
|
* Add testcase for #65Tristan Gingold2019-11-074-0/+31
|
* Add testcase from issue 1001Tristan Gingold2019-11-063-0/+82
|
* testsuite: reduce verbosity.Tristan Gingold2019-11-063-4/+4
|
* testsuite: add xfail1 testTristan Gingold2019-11-054-0/+37
|
* testsuite: add case for issue 999Tristan Gingold2019-11-052-0/+43
|
* testsuite.sh: simplify (only sub sub dirs).Tristan Gingold2019-11-051-21/+3
|
* testsuite: move pr tests in issues/Tristan Gingold2019-11-0510-17/+28
|
* testsuite: move tests of examples in a subdir.Tristan Gingold2019-11-057-43/+43
|
* testsuite: add issue1000Tristan Gingold2019-11-052-0/+51
|
* testsuite: add synth_ice40 (from synth), add synth_import.Tristan Gingold2019-11-051-2/+14
|
* testenv: use abs_topdir for default ghdl.so path.Tristan Gingold2019-11-051-1/+8
|
* Add testcase for #68Tristan Gingold2019-11-042-0/+31
|
* testsuite: it is now possible to run a single test.Tristan Gingold2019-11-0414-11/+32
|
* Add Id_Smod support (#66)Anton Blanchard2019-11-033-0/+27
|
* add iadff (#67)Pepijn de Vos2019-11-031-1/+8
|
* rewrite import_memory, directly generate $memTristan Gingold2019-11-031-97/+130
|
* handle formal input ports.Tristan Gingold2019-10-311-5/+31
|
* Handle Id_Cover_AssertTristan Gingold2019-10-221-0/+2
|
* Initial support of memories.Tristan Gingold2019-10-191-18/+152
|
* Sign extend 32b literals (#61)Pepijn de Vos2019-10-163-4/+78
| | | | | | | | | | | | | | | | | | | * sign extend 32b literals * Fix undefined behavior Right shift of a signed values is undefined but does arithemetic shift in practice. However, shifting by more than one int width is also undefined but *wraps around*. This caused bit/log to work because it'd shift mod 32. But it actually cause the UL32 to be wrong because it'd just repeat the value rather than extending. * zero pad unsigned and add signed * add testsuite
* Add Id_Neg support (#63)Anton Blanchard2019-10-163-0/+27
| | | | | | | | * Add Id_Neg support * Add testcase for Id_Neg Thanks to Pepijn for the example I based this on.
* Add Id_Smul and Id_Umul (#64)Anton Blanchard2019-10-163-0/+34
| | | | | | * Add Id_Smul and Id_Umul support * Add testcase for Id_Smul and Id_Umul
* Fix a couple of compiler warnings (#62)Anton Blanchard2019-10-141-3/+3
| | | | | | | | | | | | | | | | | I see a few compiler warnings on gcc 9.2: src/ghdl.cc: In function ‘Yosys::RTLIL::SigSpec get_src(std::vector<Yosys::RTLIL::Wire*>&, GhdlSynth::Net)’: src/ghdl.cc:123:43: warning: ‘valzx’ may be used uninitialized in this function [-Wmaybe-uninitialized] 123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2) | ~~~~~~~^~~~~ src/ghdl.cc:123:26: warning: ‘val01’ may be used uninitialized in this function [-Wmaybe-uninitialized] 123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2) | ~~~~~~~^~~~~ src/ghdl.cc:99:26: warning: ‘val’ may be used uninitialized in this function [-Wmaybe-uninitialized] 99 | bits[i] = (val >> i) & 1 ? RTLIL::State::S1 : RTLIL::State::S0; | ~~~~~^~~~~ These both appear to be spurious, but initialize them to 0 to avoid the warning.
* Handle Id_Sextend (#59)T. Meissner2019-10-091-0/+8
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 17:40:00 +0000