aboutsummaryrefslogtreecommitdiffstats
path: root/src/ghdl.cc
Commit message (Collapse)AuthorAgeFilesLines
* ghdl.cc: handle gclk attributes on dff. For ghdl/ghdl#1610Tristan Gingold2021-01-251-13/+70
| | | | Also attribute nets.
* Minor rework on attributes.Tristan Gingold2021-01-251-5/+19
|
* Use ':' instead of '$' for number namesTristan Gingold2020-11-181-2/+3
|
* ghdl.cc: allow extended identifier of length 1Tristan Gingold2020-11-181-1/+1
|
* Try to convert extended name to a nameTristan Gingold2020-11-181-1/+31
|
* '%' is not supported by Xilinx ISE edif2ngc. Fix #134eine2020-10-021-1/+2
| | | | Authored-By: Tristan Gingold <tgingold@free.fr>
* Fix signed modulo behaviourXiretza2020-05-301-4/+5
| | | | | | | | | Yosys' $mod cell is the modulo of truncating division, known as "rem" in VHDL. The new $modfloor cell is the modulo of flooring division, known as "mod" in VHDL. "mod" now synthesizes correctly for negative numbers.
* Add reduce_xor support to the Yosys pluginrlee2872020-05-281-0/+4
| | | | This is a followup for ghdl/ghdl issue 1342
* ghdl.cc: import attributes on memory. For ghdl/ghdl#1318Tristan Gingold2020-05-231-1/+19
|
* ghdl.cc: handle Id_IinoutTristan Gingold2020-05-161-0/+2
|
* Fix ordering of $pmux portsXiretza2020-05-141-2/+2
| | | | | | | | For Id_Pmux, IN(2+n) corresponds to s(n). For $pmux, B[n*WIDTH-1:(n-1)*WIDTH] corresponds to S[n]. Therefore, the inputs need to be appended in ascending order, such that IN(2) is assigned to B[WIDTH-1:0], IN(3) to B[2*WIDTH-1:WIDTH], etc.
* ghdl.cc: implement id_pmuxTristan Gingold2020-05-091-12/+22
|
* handle Id_Tri and Id_ResolverTristan Gingold2020-04-231-0/+9
|
* ghdl.cc: adjust for recent yosys. Fix #107Tristan Gingold2020-04-231-1/+1
|
* ghdl.cc: adjust for edge handle (ghdl#1227)Tristan Gingold2020-04-151-16/+53
|
* ghdl.cc: avoid duplicate blackboxes.Tristan Gingold2020-04-091-1/+4
|
* Add support for non-constant asynchronous reset dff.Tristan Gingold2020-04-071-5/+29
|
* Add support for smod. Fix #102Tristan Gingold2020-04-071-0/+2
|
* Handle Id_User_Parameters: add parameters to gates.Tristan Gingold2020-03-311-21/+60
| | | | This allows easy interfacing with verilog modules.
* Add support for inout gate. Fix #96Tristan Gingold2020-03-291-3/+39
|
* Add min/max gatesXiretza2020-03-221-0/+21
|
* Add abs gate (#91)Xiretza2020-03-101-0/+9
|
* Fix ghdl.cc indentation (#90)Xiretza2020-03-101-168/+169
| | | | Switched everything to tabs, since those seemed to be most common. Also added a vim modeline.
* ghdl.cc: avoid infinite recursion due to concatenation.Tristan Gingold2020-03-091-2/+50
|
* ghdl.cc: refactoring before optimization.Tristan Gingold2020-03-091-25/+26
|
* ghdl.cc: rewrite help.Tristan Gingold2020-03-011-2/+23
|
* ghdl.cc: adjust after changes in ghdl (for memories).Tristan Gingold2020-02-231-4/+16
|
* add cons_0, div, and umod (#72)Pepijn de Vos2019-12-311-2/+22
| | | | | | * add cons_0, [su]div, and umod * Yosys mod is actually remainder semantics
* handle mem_rd_sync gates.Tristan Gingold2019-12-051-0/+10
|
* Handle removal of id_output gates.Tristan Gingold2019-12-051-28/+10
|
* Fix init input for iadff. For #76Tristan Gingold2019-12-031-1/+1
|
* Do not rename ports. Fix #75Tristan Gingold2019-12-031-8/+9
|
* Support multiple synthesis. Fix #73Tristan Gingold2019-12-021-4/+7
|
* Add Id_Smod support (#66)Anton Blanchard2019-11-031-0/+4
|
* add iadff (#67)Pepijn de Vos2019-11-031-1/+8
|
* rewrite import_memory, directly generate $memTristan Gingold2019-11-031-97/+130
|
* handle formal input ports.Tristan Gingold2019-10-311-5/+31
|
* Handle Id_Cover_AssertTristan Gingold2019-10-221-0/+2
|
* Initial support of memories.Tristan Gingold2019-10-191-18/+152
|
* Sign extend 32b literals (#61)Pepijn de Vos2019-10-161-4/+51
| | | | | | | | | | | | | | | | | | | * sign extend 32b literals * Fix undefined behavior Right shift of a signed values is undefined but does arithemetic shift in practice. However, shifting by more than one int width is also undefined but *wraps around*. This caused bit/log to work because it'd shift mod 32. But it actually cause the UL32 to be wrong because it'd just repeat the value rather than extending. * zero pad unsigned and add signed * add testsuite
* Add Id_Neg support (#63)Anton Blanchard2019-10-161-0/+4
| | | | | | | | * Add Id_Neg support * Add testcase for Id_Neg Thanks to Pepijn for the example I based this on.
* Add Id_Smul and Id_Umul (#64)Anton Blanchard2019-10-161-0/+8
| | | | | | * Add Id_Smul and Id_Umul support * Add testcase for Id_Smul and Id_Umul
* Fix a couple of compiler warnings (#62)Anton Blanchard2019-10-141-3/+3
| | | | | | | | | | | | | | | | | I see a few compiler warnings on gcc 9.2: src/ghdl.cc: In function ‘Yosys::RTLIL::SigSpec get_src(std::vector<Yosys::RTLIL::Wire*>&, GhdlSynth::Net)’: src/ghdl.cc:123:43: warning: ‘valzx’ may be used uninitialized in this function [-Wmaybe-uninitialized] 123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2) | ~~~~~~~^~~~~ src/ghdl.cc:123:26: warning: ‘val01’ may be used uninitialized in this function [-Wmaybe-uninitialized] 123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2) | ~~~~~~~^~~~~ src/ghdl.cc:99:26: warning: ‘val’ may be used uninitialized in this function [-Wmaybe-uninitialized] 99 | bits[i] = (val >> i) & 1 ? RTLIL::State::S1 : RTLIL::State::S0; | ~~~~~^~~~~ These both appear to be spurious, but initialize them to 0 to avoid the warning.
* Handle Id_Sextend (#59)T. Meissner2019-10-091-0/+8
|
* Handle Id_Asr (#55)T. Meissner2019-10-061-0/+4
|
* add shift functions (#54)Pepijn de Vos2019-10-061-0/+8
|
* Handle Const_X & Const_Z (#49)T. Meissner2019-10-051-0/+12
|
* handle Const_LogTristan Gingold2019-10-021-25/+34
|
* Handle Const_Bit.Tristan Gingold2019-10-021-0/+14
|
* Handle covers (#43)T. Meissner2019-09-201-0/+4
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 00:03:30 +0000