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authorTristan Gingold <tgingold@free.fr>2016-09-24 21:00:28 +0200
committerTristan Gingold <tgingold@free.fr>2016-09-24 21:01:02 +0200
commit01f485580d90cdea224e15aa3d583f5c987d2c77 (patch)
tree0680032d3298bfd28577b7d41776bea71c246b48
parentdac1e0e98515cf737ba768510329159028dd1c58 (diff)
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Add testcase for issue #148
-rw-r--r--testsuite/gna/issue148/bug_sim.vhdl17
-rwxr-xr-xtestsuite/gna/issue148/testsuite.sh9
2 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/gna/issue148/bug_sim.vhdl b/testsuite/gna/issue148/bug_sim.vhdl
new file mode 100644
index 000000000..2a27adcc0
--- /dev/null
+++ b/testsuite/gna/issue148/bug_sim.vhdl
@@ -0,0 +1,17 @@
+entity bug is
+ port(data: out integer);
+end entity bug;
+
+architecture arc of bug is
+begin
+end architecture arc;
+
+entity bug_sim is
+end entity bug_sim;
+
+architecture sim of bug_sim is
+ signal data: natural;
+begin
+ u0: entity work.bug
+ port map(data => data);
+end architecture sim;
diff --git a/testsuite/gna/issue148/testsuite.sh b/testsuite/gna/issue148/testsuite.sh
new file mode 100755
index 000000000..baa136e35
--- /dev/null
+++ b/testsuite/gna/issue148/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze bug_sim.vhdl
+elab_failure bug_sim
+clean
+
+echo "Test successful"