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author | Tristan Gingold <tgingold@free.fr> | 2017-10-30 05:45:23 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-10-30 05:45:23 +0100 |
commit | 3f4ad3263f7e5294e20166c1396db48826a4bda5 (patch) | |
tree | f9d28d9e485b1c8620cde18f5602e75a53d27d11 | |
parent | bc96278e27150ad85ab73e08b7236f2a4198205d (diff) | |
download | ghdl-3f4ad3263f7e5294e20166c1396db48826a4bda5.tar.gz ghdl-3f4ad3263f7e5294e20166c1396db48826a4bda5.tar.bz2 ghdl-3f4ad3263f7e5294e20166c1396db48826a4bda5.zip |
Add testcase for previous commit.
-rw-r--r-- | testsuite/gna/bug079/repro1.vhdl | 19 | ||||
-rw-r--r-- | testsuite/gna/bug079/repro2.vhdl | 25 | ||||
-rwxr-xr-x | testsuite/gna/bug079/testsuite.sh | 13 |
3 files changed, 57 insertions, 0 deletions
diff --git a/testsuite/gna/bug079/repro1.vhdl b/testsuite/gna/bug079/repro1.vhdl new file mode 100644 index 000000000..08d122f1f --- /dev/null +++ b/testsuite/gna/bug079/repro1.vhdl @@ -0,0 +1,19 @@ +entity repro1 is +end repro1; + +architecture behav of repro1 is +begin + + process + variable var : natural; + + procedure proc (var : natural) is + begin + assert var = 5; + end; + begin + var := 5; + proc (var => var); + wait; + end process; +end behav; diff --git a/testsuite/gna/bug079/repro2.vhdl b/testsuite/gna/bug079/repro2.vhdl new file mode 100644 index 000000000..d1cec45bb --- /dev/null +++ b/testsuite/gna/bug079/repro2.vhdl @@ -0,0 +1,25 @@ +entity repro2 is +end repro2; + +architecture behav of repro2 is +begin + + process + type my_rec is record + inc : natural; + b : bit; + end record; + + constant bv : bit_vector := x"45"; + + procedure proc (v : my_rec; bv : bit) is + begin + assert v.b = bv; + end; + begin + proc (v => (inc => 3, + b => bv(3)), + bv => '0'); + wait; + end process; +end behav; diff --git a/testsuite/gna/bug079/testsuite.sh b/testsuite/gna/bug079/testsuite.sh new file mode 100755 index 000000000..e9441fcef --- /dev/null +++ b/testsuite/gna/bug079/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze repro1.vhdl +elab_simulate repro1 + +analyze repro2.vhdl +elab_simulate repro2 + +clean + +echo "Test successful" |