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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-30 04:17:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-30 04:17:12 +0200 |
| commit | 42bda91d39ff6aa94bedc116e495995e66e7559e (patch) | |
| tree | becb645825f85755dbffa28dbe16b4692ef11ad6 | |
| parent | 0599fde14e1032fb3bfbbe4fe26aba874070a826 (diff) | |
| download | ghdl-42bda91d39ff6aa94bedc116e495995e66e7559e.tar.gz ghdl-42bda91d39ff6aa94bedc116e495995e66e7559e.tar.bz2 ghdl-42bda91d39ff6aa94bedc116e495995e66e7559e.zip | |
synth: handle std_logic_unsigned."+"
| -rw-r--r-- | src/synth/synth-expr.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 9 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 6 |
3 files changed, 17 insertions, 1 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index c7100d29e..fdbccadaa 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -712,7 +712,8 @@ package body Synth.Expr is when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat => -- "+" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Id_Add); - when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns => + when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl => -- "+" (Unsigned, Unsigned) return Synth_Dyadic_Uns (Id_Add, True); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 643c75ddd..9fbdac603 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -33,6 +33,13 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv, others => Iir_Predefined_None); + Add_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv, + Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, + Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv); + Error : exception; procedure Extract_Declarations (Pkg : Iir_Package_Declaration) @@ -107,6 +114,8 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is case Get_Identifier (Decl) is when Name_Op_Equality => Handle_Binary (Eq_Patterns); + when Name_Op_Plus => + Handle_Binary (Add_Patterns); when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 84d8a7525..2e9e8c049 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4880,6 +4880,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Math_Real_Log2, -- Std_Logic_Unsigned (synopsys extension). + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv |