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| author | Tristan Gingold <tgingold@free.fr> | 2023-02-11 13:33:42 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-02-11 13:33:42 +0100 |
| commit | 5b6835c11fb82aba91cbde3a5900ce5a45dfe725 (patch) | |
| tree | 17ffe4b44347ca88ce22c0abbfb79da007b026db | |
| parent | 5bb3160559d2180f6300e21cf5bd853b63b32d37 (diff) | |
| download | ghdl-5b6835c11fb82aba91cbde3a5900ce5a45dfe725.tar.gz ghdl-5b6835c11fb82aba91cbde3a5900ce5a45dfe725.tar.bz2 ghdl-5b6835c11fb82aba91cbde3a5900ce5a45dfe725.zip | |
vhdl-sem_lib: units during analysis can depend only on analyzed units.
| -rw-r--r-- | src/vhdl/vhdl-sem_lib.adb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-sem_lib.adb b/src/vhdl/vhdl-sem_lib.adb index b7e5b6d1d..f8f17491c 100644 --- a/src/vhdl/vhdl-sem_lib.adb +++ b/src/vhdl/vhdl-sem_lib.adb @@ -297,6 +297,8 @@ package body Vhdl.Sem_Lib is while Is_Valid (It) loop El := Get_Element (It); if Get_Kind (El) = Iir_Kind_Design_Unit then + -- TODO: If both units are in the same library, a better check + -- would be comparing dates. U_Ts := Get_Analysis_Time_Stamp (Get_Design_File (El)); if Files_Map.Is_Gt (U_Ts, Du_Ts) then Error_Obsolete @@ -353,6 +355,10 @@ package body Vhdl.Sem_Lib is if Get_Date (Design_Unit) = Date_Replacing then Error_Msg_Sem (+Loc, "circular reference of %n", +Design_Unit); return; + elsif not Flags.Flag_Elaborate_With_Outdated + and then Get_Date (Design_Unit) = Date_Parsed + then + Error_Msg_Sem (+Loc, "unit %n has not been analyzed", +Design_Unit); end if; -- Save and clear Nbr_Errors so that the unit is fully analyzed even |