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author | Tristan Gingold <tgingold@free.fr> | 2022-10-02 11:46:21 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-10-02 11:47:37 +0200 |
commit | 7ebccfbd51085218014940f3b063b45c193f1eb5 (patch) | |
tree | 122ea579c485462aeb1b350ca21eb7e8388da769 | |
parent | da679767f9a25def8673bda1fe6cdc9e5047f990 (diff) | |
download | ghdl-7ebccfbd51085218014940f3b063b45c193f1eb5.tar.gz ghdl-7ebccfbd51085218014940f3b063b45c193f1eb5.tar.bz2 ghdl-7ebccfbd51085218014940f3b063b45c193f1eb5.zip |
synth: detect division by 0, handle universal real/integer division
-rw-r--r-- | src/synth/synth-vhdl_eval.adb | 26 |
1 files changed, 23 insertions, 3 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 46387c906..1817794cc 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -490,12 +490,18 @@ package body Synth.Vhdl_Eval is return Create_Memory_Discrete (Res, Res_Typ); end; when Iir_Predefined_Integer_Div - | Iir_Predefined_Physical_Physical_Div - | Iir_Predefined_Physical_Integer_Div => + | Iir_Predefined_Physical_Physical_Div + | Iir_Predefined_Physical_Integer_Div => declare + Rv : Int64; Res : Int64; begin - Res := Read_Discrete (Left) / Read_Discrete (Right); + Rv := Read_Discrete (Right); + if Rv = 0 then + Error_Msg_Synth (Inst, Expr, "division by zero"); + return Null_Memtyp; + end if; + Res := Read_Discrete (Left) / Rv; Check_Integer_Overflow (Inst, Res, Res_Typ, Expr); return Create_Memory_Discrete (Res, Res_Typ); end; @@ -620,6 +626,20 @@ package body Synth.Vhdl_Eval is return Create_Memory_Fp64 (Read_Fp64 (Left) ** Integer (Read_Discrete (Right)), Res_Typ); + when Iir_Predefined_Universal_R_I_Div => + declare + Rv : Int64; + Res : Fp64; + begin + Rv := Read_Discrete (Right); + if Rv = 0 then + Error_Msg_Synth (Inst, Expr, "division by zero"); + return Null_Memtyp; + end if; + Res := Read_Fp64 (Left) / Fp64 (Rv); + return Create_Memory_Fp64 (Res, Res_Typ); + end; + when Iir_Predefined_Array_Array_Concat => declare use Flags; |