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| author | Tristan Gingold <tgingold@free.fr> | 2016-12-19 08:22:10 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-12-19 08:22:10 +0100 |
| commit | a972d7cc04e1a7b996a513a6a2e521b770651157 (patch) | |
| tree | 7bdeada25a9dc9c4938c488b25ba44f50aaadcce | |
| parent | 712e445efe3b69c2fdecec4dd472390d251541ad (diff) | |
| download | ghdl-a972d7cc04e1a7b996a513a6a2e521b770651157.tar.gz ghdl-a972d7cc04e1a7b996a513a6a2e521b770651157.tar.bz2 ghdl-a972d7cc04e1a7b996a513a6a2e521b770651157.zip | |
test perf02: reduce verbosity.
| -rw-r--r-- | testsuite/gna/perf02/tb.vhd | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/gna/perf02/tb.vhd b/testsuite/gna/perf02/tb.vhd index e79a1d842..135b2612c 100644 --- a/testsuite/gna/perf02/tb.vhd +++ b/testsuite/gna/perf02/tb.vhd @@ -148,7 +148,7 @@ begin clock_counter <= clock_counter + 1; - if simu_disp_cycles = '1' then + if false and simu_disp_cycles = '1' then -- Write simulation message write(l, string'("INFO clock cycle ")); write(l, clock_counter); |