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authorTristan Gingold <tgingold@free.fr>2018-12-18 06:35:42 +0100
committerTristan Gingold <tgingold@free.fr>2018-12-18 07:36:25 +0100
commitd8b1335eb3be3e0e6b3fe38344cc7fa3d99a59d7 (patch)
tree5c462842214b008e6faa96757319b4dd2e66f088
parentcb79d295c4bdf498e602a3f7e2875613c80ed8d9 (diff)
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sanity: test examples from the doc.
-rw-r--r--testsuite/sanity/005examples/extract_vhdl.py30
-rw-r--r--testsuite/sanity/005examples/hdl-prj.json8
-rwxr-xr-xtestsuite/sanity/005examples/testsuite.sh20
3 files changed, 58 insertions, 0 deletions
diff --git a/testsuite/sanity/005examples/extract_vhdl.py b/testsuite/sanity/005examples/extract_vhdl.py
new file mode 100644
index 000000000..fa2243caa
--- /dev/null
+++ b/testsuite/sanity/005examples/extract_vhdl.py
@@ -0,0 +1,30 @@
+#!/usr/bin/env python
+import sys
+
+def extract(out):
+ # Skip until the first line
+ while (1):
+ l = sys.stdin.readline()
+ if l == '':
+ return False
+ if l == '.. code-block:: VHDL\n':
+ break
+
+ # Write example
+ while (1):
+ l = sys.stdin.readline()
+ if l[0] == '\n':
+ out.write(l)
+ elif len(l) >= 2 and l[:2] == ' ':
+ out.write(l[2:])
+ else:
+ break
+
+ return True
+
+for f in sys.argv[1:]:
+ print("Extracting {}...".format(f))
+ with open(f, "w") as out:
+ if not extract(out):
+ sys.exit(1)
+sys.exit(0)
diff --git a/testsuite/sanity/005examples/hdl-prj.json b/testsuite/sanity/005examples/hdl-prj.json
new file mode 100644
index 000000000..9895e7de0
--- /dev/null
+++ b/testsuite/sanity/005examples/hdl-prj.json
@@ -0,0 +1,8 @@
+{
+ "files": [
+ { "name": "adder.vhdl", "language": "vhdl"},
+ { "name": "adder_tb.vhdl", "language": "vhdl"},
+ { "name": "heartbeat.vhdl", "language": "vhdl"},
+ { "name": "hello.vhdl", "language": "vhdl"}
+ ]
+}
diff --git a/testsuite/sanity/005examples/testsuite.sh b/testsuite/sanity/005examples/testsuite.sh
new file mode 100755
index 000000000..2cf61446f
--- /dev/null
+++ b/testsuite/sanity/005examples/testsuite.sh
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+. ../../testenv.sh
+
+# Extract examples
+python extract_vhdl.py hello.vhdl heartbeat.vhdl adder.vhdl adder_tb.vhdl < ../../../doc/using/QuickStartGuide.rst
+
+analyze hello.vhdl
+elab_simulate hello_world
+
+analyze heartbeat.vhdl
+elab_simulate heartbeat --stop-time=100ns
+
+analyze adder.vhdl
+analyze adder_tb.vhdl
+elab_simulate adder_tb
+
+clean
+
+echo "test successful"