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author | umarcor <unai.martinezcorral@ehu.eus> | 2021-01-05 22:34:14 +0100 |
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committer | umarcor <unai.martinezcorral@ehu.eus> | 2021-02-01 09:25:35 +0100 |
commit | 75ef931f4a7a0a4f3ddca1727d6f63ea6f4d2482 (patch) | |
tree | 3696139763213050943781d144a18272a24997c2 /doc/quick_start/heartbeat | |
parent | 835eb73d7c567c3178f6f693153bea3243ecef53 (diff) | |
download | ghdl-75ef931f4a7a0a4f3ddca1727d6f63ea6f4d2482.tar.gz ghdl-75ef931f4a7a0a4f3ddca1727d6f63ea6f4d2482.tar.bz2 ghdl-75ef931f4a7a0a4f3ddca1727d6f63ea6f4d2482.zip |
doc: reorganise and update
Diffstat (limited to 'doc/quick_start/heartbeat')
-rw-r--r-- | doc/quick_start/heartbeat/README.rst | 42 | ||||
-rw-r--r-- | doc/quick_start/heartbeat/heartbeat.vhdl | 20 |
2 files changed, 0 insertions, 62 deletions
diff --git a/doc/quick_start/heartbeat/README.rst b/doc/quick_start/heartbeat/README.rst deleted file mode 100644 index e95145095..000000000 --- a/doc/quick_start/heartbeat/README.rst +++ /dev/null @@ -1,42 +0,0 @@ -.. program:: ghdl -.. _QuickStart:heartbeat: - -`Heartbeat` module -================== - -Although :ref:`Hello world <QuickStart:hello>` illustrates that `VHDL` is supported as a general purpose language, the main use case -of `GHDL` is to simulate hardware descriptions. The following block, which is saved in a file named -:file:`heartbeat.vhdl`, is an example of how to generate a 100 MHz clock signal with non-synthesisable VHDL: - -.. literalinclude:: heartbeat.vhdl - :language: vhdl - -It can be :ref:`analysed <Analysis:command>`, :ref:`elaborated <Elaboration:command>` and :ref:`run <Run:command>`, as you already know: - -.. code-block:: shell - - ghdl -a heartbeat.vhdl - ghdl -e heartbeat - ghdl -r heartbeat - -However, execution of the design does not terminate. At the same time, no output is shown on screen. This is because, -traditionally, hardware designs are continuously running devices which do not have a screen where to print. In this -context, inspection and verification of the behaviour is done through `waveforms <https://en.wikipedia.org/wiki/Waveform_viewer>`_, -which is supported by `GHDL` (see :ref:`export_waves`). You can use either :option:`--wave`, :option:`--vcd`, -:option:`--vcdgz` or :option:`--fst` to save the signals of the simulation to a file. Then, terminate the execution -(:kbd:`C-c`) and you can inspect the wave with a viewer, such as `GtkWave <http://gtkwave.sourceforge.net/>`_. As -explained in the `manual <http://gtkwave.sourceforge.net/gtkwave.pdf>`_, GtkWave *'relies on a post-mortem approach -through the use of dumpfiles'*. Therefore, you should first simulate your design and dump a waveform file, say GHW: - -.. code-block:: shell - - ghdl -r heartbeat --wave=wave.ghw - -Then, you can view the dump: - -.. code-block:: shell - - gtkwave wave.ghw - -Of course, manually terminating the simulation is for illustration purposes only. In :ref:`Full adder <QuickStart:adder>` and -:ref:`QuickStart:DLX`, you will see how to write a testbench to terminate the simulation programmatically. diff --git a/doc/quick_start/heartbeat/heartbeat.vhdl b/doc/quick_start/heartbeat/heartbeat.vhdl deleted file mode 100644 index 0a312641e..000000000 --- a/doc/quick_start/heartbeat/heartbeat.vhdl +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity heartbeat is - port ( clk: out std_logic); -end heartbeat; - -architecture behaviour of heartbeat -is - constant clk_period : time := 10 ns; -begin - -- Clock process definition - clk_process: process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; -end behaviour; |