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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-13 19:20:43 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-13 19:20:43 +0100 |
| commit | a13ef8cc10b50432300f2d376bcfa8fff24351b7 (patch) | |
| tree | ccaa0fe5a8a526333f2234a75206a7fd1d8d1466 /python/libghdl | |
| parent | 2143539b0943bc0917cb485c4571b8f9efe9df7f (diff) | |
| download | ghdl-a13ef8cc10b50432300f2d376bcfa8fff24351b7.tar.gz ghdl-a13ef8cc10b50432300f2d376bcfa8fff24351b7.tar.bz2 ghdl-a13ef8cc10b50432300f2d376bcfa8fff24351b7.zip | |
vhdl: recognize more std_logic_arith operations.
Diffstat (limited to 'python/libghdl')
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 2da9debfd..82baa62c8 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1409,6 +1409,38 @@ class Iir_Predefined: Ieee_Std_Logic_Arith_Conv_Vector_Uns = 426 Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 427 Ieee_Std_Logic_Arith_Conv_Vector_Log = 428 + Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 429 + Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 430 + Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 431 + Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 432 + Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 433 + Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 434 + Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 435 + Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 436 + Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 437 + Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 438 + Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 439 + Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 440 + Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 441 + Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 442 + Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 443 + Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 444 + Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 445 + Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 446 + Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 447 + Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 448 + Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 449 + Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 450 + Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 451 + Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 452 + Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 453 + Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 454 + Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 455 + Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 456 + Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 457 + Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 458 + Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 459 + Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 460 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location |