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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:20:30 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:20:30 +0200 |
| commit | 688173587e76ee89b67b0c0aeb93385c0db08b22 (patch) | |
| tree | 5d9fda9535196719ac8a71f90d1a2d62529d42f0 /python | |
| parent | 17ab141656d8a0ba80309ca4d85e65a038c873e0 (diff) | |
| download | ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.tar.gz ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.tar.bz2 ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.zip | |
vhdl: rename Cover_Statement to Cover_Directive.
Diffstat (limited to 'python')
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 90e0339cf..101e6500b 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -268,7 +268,7 @@ class Iir_Kind: Concurrent_Assertion_Statement = 183 Concurrent_Procedure_Call_Statement = 184 Psl_Assert_Statement = 185 - Psl_Cover_Statement = 186 + Psl_Cover_Directive = 186 Psl_Restrict_Directive = 187 >>>>>>> vhdl: parse and analyze restrict directive. Block_Statement = 188 @@ -528,7 +528,7 @@ class Iir_Kinds: Iir_Kind.Concurrent_Assertion_Statement, Iir_Kind.Concurrent_Procedure_Call_Statement, Iir_Kind.Psl_Assert_Statement, - Iir_Kind.Psl_Cover_Statement, + Iir_Kind.Psl_Cover_Directive, Iir_Kind.Psl_Restrict_Directive] Non_Alias_Object_Declaration = [ @@ -720,7 +720,7 @@ class Iir_Kinds: Iir_Kind.Concurrent_Assertion_Statement, Iir_Kind.Concurrent_Procedure_Call_Statement, Iir_Kind.Psl_Assert_Statement, - Iir_Kind.Psl_Cover_Statement, + Iir_Kind.Psl_Cover_Directive, Iir_Kind.Psl_Restrict_Directive, Iir_Kind.Block_Statement, Iir_Kind.If_Generate_Statement, |