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author | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:00:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:05:12 +0200 |
commit | 3fa8d9eb8b700044d149bdf12da6cb023568b8c0 (patch) | |
tree | 3cbd54423bad53e6db401e43ef0e4216833cd8b9 /src/ghdldrv | |
parent | 85d360929d13e6b0bcb082f144883a43f402ce22 (diff) | |
download | ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.tar.gz ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.tar.bz2 ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.zip |
vhdl: move ieee packages to vhdl children.
Diffstat (limited to 'src/ghdldrv')
-rw-r--r-- | src/ghdldrv/ghdldrv.adb | 6 | ||||
-rw-r--r-- | src/ghdldrv/ghdlrun.adb | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/ghdldrv/ghdldrv.adb b/src/ghdldrv/ghdldrv.adb index d6e2210ac..0d14c8035 100644 --- a/src/ghdldrv/ghdldrv.adb +++ b/src/ghdldrv/ghdldrv.adb @@ -23,7 +23,7 @@ with Tables; with GNAT.Dynamic_Tables; with Libraries; with Name_Table; use Name_Table; -with Std_Package; +with Vhdl.Std_Package; with Types; use Types; with Iirs; use Iirs; with Files_Map; @@ -1570,7 +1570,7 @@ package body Ghdldrv is while Is_Valid (Files_It) loop File := Get_Element (Files_It); - if File = Std_Package.Std_Standard_File then + if File = Vhdl.Std_Package.Std_Standard_File then Need_Analyze := False; elsif Missing_Object_File (File) or else Source_File_Modified (File) @@ -1710,7 +1710,7 @@ package body Ghdldrv is function Is_Makeable_File (File : Iir_Design_File) return Boolean is begin - if File = Std_Package.Std_Standard_File then + if File = Vhdl.Std_Package.Std_Standard_File then return False; end if; return True; diff --git a/src/ghdldrv/ghdlrun.adb b/src/ghdldrv/ghdlrun.adb index f8b3adaaf..fc59d0e7e 100644 --- a/src/ghdldrv/ghdlrun.adb +++ b/src/ghdldrv/ghdlrun.adb @@ -40,7 +40,7 @@ with Vhdl.Canon; with Vhdl.Configuration; with Trans_Be; with Translation; -with Ieee.Std_Logic_1164; +with Vhdl.Ieee.Std_Logic_1164; with Lists; with Str_Table; @@ -738,9 +738,9 @@ package body Ghdlrun is Ortho_Jit.Get_Address (Trans_Decls.Std_Standard_Boolean_Rti); Grtlink.Std_Standard_Bit_RTI_Ptr := Ortho_Jit.Get_Address (Trans_Decls.Std_Standard_Bit_Rti); - if Ieee.Std_Logic_1164.Resolved /= Null_Iir then + if Vhdl.Ieee.Std_Logic_1164.Resolved /= Null_Iir then Decl := Translation.Get_Resolv_Ortho_Decl - (Ieee.Std_Logic_1164.Resolved); + (Vhdl.Ieee.Std_Logic_1164.Resolved); if Decl /= O_Dnode_Null then Grtlink.Ieee_Std_Logic_1164_Resolved_Resolv_Ptr := Ortho_Jit.Get_Address (Decl); |