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author | Tristan Gingold <tgingold@free.fr> | 2016-07-03 16:30:36 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-07-03 16:34:21 +0200 |
commit | 84c47a11b41af9f9c54ae8b78f6fc0bbe087c3c0 (patch) | |
tree | 84d0cf43d0b036772a1f48477bf486c38b41d159 /src/grt/grt-vcd.ads | |
parent | 3f72c841aba4555ba511c303074ffb2896e9551e (diff) | |
download | ghdl-84c47a11b41af9f9c54ae8b78f6fc0bbe087c3c0.tar.gz ghdl-84c47a11b41af9f9c54ae8b78f6fc0bbe087c3c0.tar.bz2 ghdl-84c47a11b41af9f9c54ae8b78f6fc0bbe087c3c0.zip |
vpi: handle parameters/generics.
Diffstat (limited to 'src/grt/grt-vcd.ads')
-rw-r--r-- | src/grt/grt-vcd.ads | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/grt/grt-vcd.ads b/src/grt/grt-vcd.ads index 566901dfc..6253a4323 100644 --- a/src/grt/grt-vcd.ads +++ b/src/grt/grt-vcd.ads @@ -23,10 +23,10 @@ -- however invalidate any other reasons why the executable file might be -- covered by the GNU Public License. +with System; with Grt.Types; use Grt.Types; with Grt.Avhpi; use Grt.Avhpi; with Grt.Rtis; -with Grt.Signals; package Grt.Vcd is -- Abstract type for IO. @@ -67,13 +67,17 @@ package Grt.Vcd is range Vcd_Bitvector .. Vcd_Stdlogic_Vector; -- Which value to be displayed: effective or driving (for out signals). - type Vcd_Value_Kind is (Vcd_Effective, Vcd_Driving); + type Vcd_Value_Kind is (Vcd_Effective, Vcd_Driving, Vcd_Variable); + + -- For signals. + subtype Vcd_Value_Signals is Vcd_Value_Kind + range Vcd_Effective .. Vcd_Driving; type Verilog_Wire_Info (Vtype : Vcd_Var_Type := Vcd_Bad) is record Val : Vcd_Value_Kind; - -- Access to an array of signals. - Sigs : Grt.Signals.Signal_Arr_Ptr; + -- Access to an array of signals or access to the value. + Ptr : System.Address; case Vtype is when Vcd_Var_Vectors => @@ -102,5 +106,10 @@ package Grt.Vcd is -- Return TRUE if there is an event on the wire, for the current cycle. function Verilog_Wire_Event (Info : Verilog_Wire_Info) return Boolean; + -- Return a pointer to the value of a wire. + function Verilog_Wire_Val (Info : Verilog_Wire_Info) return Ghdl_Value_Ptr; + function Verilog_Wire_Val (Info : Verilog_Wire_Info; Idx : Ghdl_Index_Type) + return Ghdl_Value_Ptr; + procedure Register; end Grt.Vcd; |