diff options
| author | Tristan Gingold <tgingold@free.fr> | 2014-12-01 06:09:00 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2014-12-01 06:09:00 +0100 |
| commit | a30f7137ff1efe33174f840e3fe16d35cd554d97 (patch) | |
| tree | d050ec0374a19cf939dc6b200c55421a0e425ee1 /src/grt/grt-vpi.adb | |
| parent | f75810293f0b1d43ba7492fd774a75ee7872584e (diff) | |
| download | ghdl-a30f7137ff1efe33174f840e3fe16d35cd554d97.tar.gz ghdl-a30f7137ff1efe33174f840e3fe16d35cd554d97.tar.bz2 ghdl-a30f7137ff1efe33174f840e3fe16d35cd554d97.zip | |
grt-vcd: in verilog_wire_info, replace addr by sigs.
Diffstat (limited to 'src/grt/grt-vpi.adb')
| -rw-r--r-- | src/grt/grt-vpi.adb | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/src/grt/grt-vpi.adb b/src/grt/grt-vpi.adb index 9b77319f1..37cc714f6 100644 --- a/src/grt/grt-vpi.adb +++ b/src/grt/grt-vpi.adb @@ -424,14 +424,12 @@ package body Grt.Vpi is | Vcd_Bool | Vcd_Bitvector => for J in 0 .. Len - 1 loop - ii_vpi_get_value_bin_str_B1 - (To_Signal_Arr_Ptr (Info.Addr)(J).Value.B1); + ii_vpi_get_value_bin_str_B1 (Info.Sigs (J).Value.B1); end loop; when Vcd_Stdlogic | Vcd_Stdlogic_Vector => for J in 0 .. Len - 1 loop - ii_vpi_get_value_bin_str_E8 - (To_Signal_Arr_Ptr (Info.Addr)(J).Value.E8); + ii_vpi_get_value_bin_str_E8 (Info.Sigs (J).Value.E8); end loop; end case; when Vcd_Driving => @@ -445,13 +443,13 @@ package body Grt.Vpi is | Vcd_Bitvector => for J in 0 .. Len - 1 loop ii_vpi_get_value_bin_str_B1 - (To_Signal_Arr_Ptr (Info.Addr)(J).Driving_Value.B1); + (Info.Sigs (J).Driving_Value.B1); end loop; when Vcd_Stdlogic | Vcd_Stdlogic_Vector => for J in 0 .. Len - 1 loop ii_vpi_get_value_bin_str_E8 - (To_Signal_Arr_Ptr (Info.Addr)(J).Driving_Value.E8); + (Info.Sigs (J).Driving_Value.E8); end loop; end case; end case; @@ -626,14 +624,14 @@ package body Grt.Vpi is | Vcd_Bool | Vcd_Bitvector => for J in 0 .. Len - 1 loop - ii_vpi_put_value_bin_str_B1( - To_Signal_Arr_Ptr(Info.Addr)(J), ValueStr(Integer(J+1))); + ii_vpi_put_value_bin_str_B1 + (Info.Sigs (J), ValueStr (Integer (J + 1))); end loop; when Vcd_Stdlogic | Vcd_Stdlogic_Vector => for J in 0 .. Len - 1 loop - ii_vpi_put_value_bin_str_E8( - To_Signal_Arr_Ptr(Info.Addr)(J), ValueStr(Integer(J+1))); + ii_vpi_put_value_bin_str_E8 + (Info.Sigs (J), ValueStr (Integer (J + 1))); end loop; when Vcd_Integer32 | Vcd_Float64 => |