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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 07:00:51 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 07:00:51 +0100 |
| commit | e7dba34e2b1f38f920cef3c4faed449921200668 (patch) | |
| tree | 3c104447fcfacbdb0deddd70c9e0842d47994ced /src/simul | |
| parent | 467acc26b864bd0d4e531b1095cef067ba83cf3b (diff) | |
| download | ghdl-e7dba34e2b1f38f920cef3c4faed449921200668.tar.gz ghdl-e7dba34e2b1f38f920cef3c4faed449921200668.tar.bz2 ghdl-e7dba34e2b1f38f920cef3c4faed449921200668.zip | |
synth: improve support of PSL endpoints
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 4948152cc..3e5acc3d8 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -902,7 +902,8 @@ package body Simul.Vhdl_Elab is pragma Assert (Is_Expr_Pool_Empty); Gather_Process_Sensitivity (Inst, Stmt, Processes_Table.Last); when Iir_Kind_Psl_Default_Clock - | Iir_Kind_Psl_Declaration => + | Iir_Kind_Psl_Declaration + | Iir_Kind_Psl_Endpoint_Declaration => null; when Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive |