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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-18 06:21:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-18 06:21:17 +0200 |
| commit | fe6edccd9c03f40878cc1d27b07c024407d63bff (patch) | |
| tree | 556c0f25e5179b112f1209e6f07dbfe9bd9b1d5c /src/simul | |
| parent | 0db659f0d91d57c5b36ae40c3be0f542a4ad75d1 (diff) | |
| download | ghdl-fe6edccd9c03f40878cc1d27b07c024407d63bff.tar.gz ghdl-fe6edccd9c03f40878cc1d27b07c024407d63bff.tar.bz2 ghdl-fe6edccd9c03f40878cc1d27b07c024407d63bff.zip | |
ghdlsimul: add an option to debug before elaboration
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 6 | ||||
| -rw-r--r-- | src/simul/simul-vhdl_simul.ads | 1 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index b44028c57..5d691e807 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2075,9 +2075,9 @@ package body Simul.Vhdl_Simul is -- Grt.Errors.Error_Hook := Debug_Error'Access; --- if Flag_Interractive then --- Debug (Reason_Start); --- end if; + if Flag_Debug_Elab then + Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance); + end if; Ok := Grt.Main.Run_Elab; if not Ok then diff --git a/src/simul/simul-vhdl_simul.ads b/src/simul/simul-vhdl_simul.ads index 5e837d454..a929c3fa6 100644 --- a/src/simul/simul-vhdl_simul.ads +++ b/src/simul/simul-vhdl_simul.ads @@ -37,6 +37,7 @@ package Simul.Vhdl_Simul is Trace_Simulation : Boolean := False; Flag_Interractive : Boolean := False; + Flag_Debug_Elab : Boolean := False; Trace_Residues : Boolean := False; |