2 files changed, 4 insertions, 3 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index b44028c57..5d691e807 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2075,9 +2075,9 @@ package body Simul.Vhdl_Simul is
 
 --      Grt.Errors.Error_Hook := Debug_Error'Access;
 
---      if Flag_Interractive then
---         Debug (Reason_Start);
---      end if;
+      if Flag_Debug_Elab then
+         Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
+      end if;
 
       Ok := Grt.Main.Run_Elab;
       if not Ok then
diff --git a/src/simul/simul-vhdl_simul.ads b/src/simul/simul-vhdl_simul.ads
index 5e837d454..a929c3fa6 100644
--- a/src/simul/simul-vhdl_simul.ads
+++ b/src/simul/simul-vhdl_simul.ads
@@ -37,6 +37,7 @@ package Simul.Vhdl_Simul is
    Trace_Simulation : Boolean := False;
 
    Flag_Interractive : Boolean := False;
+   Flag_Debug_Elab : Boolean := False;
 
    Trace_Residues : Boolean := False;