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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-28 18:30:22 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-28 18:30:22 +0200 |
| commit | 12e5e54325111f11d7bb6283eed7fd4a3760a899 (patch) | |
| tree | 1a392cb18edb4ec1e1a3e641cd434eb152169388 /src/std_names.ads | |
| parent | 1048f7b66fc74c09e7fc2afc2df1bac6516c9912 (diff) | |
| download | ghdl-12e5e54325111f11d7bb6283eed7fd4a3760a899.tar.gz ghdl-12e5e54325111f11d7bb6283eed7fd4a3760a899.tar.bz2 ghdl-12e5e54325111f11d7bb6283eed7fd4a3760a899.zip | |
std_names: add names for math_real.
Diffstat (limited to 'src/std_names.ads')
| -rw-r--r-- | src/std_names.ads | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/std_names.ads b/src/std_names.ads index de5af8131..44a6b8495 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -708,7 +708,10 @@ package Std_Names is Name_To_Integer : constant Name_Id := Name_First_Ieee + 019; Name_To_Unsigned : constant Name_Id := Name_First_Ieee + 020; Name_To_Signed : constant Name_Id := Name_First_Ieee + 021; - Name_Last_Ieee : constant Name_Id := Name_To_Signed; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 022; + Name_Ceil : constant Name_Id := Name_First_Ieee + 023; + Name_Log2 : constant Name_Id := Name_First_Ieee + 024; + Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_Ieee + 1; |