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authorTristan Gingold <tgingold@free.fr>2019-10-02 20:17:23 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-02 20:17:23 +0200
commitd145f8b9f99463f310a466f2e8e114d1b61afaee (patch)
treecc53ea8b73878af0cc7b2d20a41dfb700a5a3c59 /src/synth/netlists-disp_vhdl.adb
parent336dbeaa305bdfe968a500161f561b35a9c495c0 (diff)
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synth: introduce memidx1
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r--src/synth/netlists-disp_vhdl.adb15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index d83edfeec..fed799508 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -586,6 +586,21 @@ package body Netlists.Disp_Vhdl is
Disp_Template (" \o0 <= ", Inst);
Disp_Extract (Inst);
Put_Line (";");
+ when Id_Memidx1 =>
+ declare
+ O : constant Net := Get_Output (Inst, 0);
+ Wd : constant Width := Get_Width (O);
+ Step : constant Uns32 := Get_Param_Uns32 (Inst, 0);
+ begin
+ if Step /= 1 then
+ Disp_Template
+ (" \o0 <= std_logic_vector "
+ & "(resize (resize (\ui0, \n0) * \up0, \n0));"
+ & NL, Inst, (0 => Wd));
+ else
+ Disp_Template (" \o0 <= \i0;" & NL, Inst);
+ end if;
+ end;
when Id_Dyn_Extract =>
declare
O : constant Net := Get_Output (Inst, 0);