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author | Tristan Gingold <tgingold@free.fr> | 2019-10-02 20:17:23 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-02 20:17:23 +0200 |
commit | d145f8b9f99463f310a466f2e8e114d1b61afaee (patch) | |
tree | cc53ea8b73878af0cc7b2d20a41dfb700a5a3c59 /src/synth/netlists-gates.ads | |
parent | 336dbeaa305bdfe968a500161f561b35a9c495c0 (diff) | |
download | ghdl-d145f8b9f99463f310a466f2e8e114d1b61afaee.tar.gz ghdl-d145f8b9f99463f310a466f2e8e114d1b61afaee.tar.bz2 ghdl-d145f8b9f99463f310a466f2e8e114d1b61afaee.zip |
synth: introduce memidx1
Diffstat (limited to 'src/synth/netlists-gates.ads')
-rw-r--r-- | src/synth/netlists-gates.ads | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 41cb597f6..818a7eee2 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -156,7 +156,7 @@ package Netlists.Gates is -- OUT := IN0 * STEP, IN0 < MAX Id_Memidx1 : constant Module_Id := 71; - -- OUT := IN0 * STEP + IN1, IN0 < MAX + -- OUT := IN0 * STEP + IN1, IN0 < MAX, size extension. Id_Memidx2 : constant Module_Id := 72; -- Positive/rising edge detector. This is a pseudo gate. |