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| author | Tristan Gingold <tgingold@free.fr> | 2021-11-17 21:43:10 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-11-17 21:43:10 +0100 |
| commit | 29b56efcbdaea0002b4f71e229ee44c1ebe75a08 (patch) | |
| tree | 5d9792f5a8a3532f695a83f20b3e4cf54fc71b5e /src/synth/netlists.adb | |
| parent | d6f1c6a47fb8df07fca517fb68078c324c761a97 (diff) | |
| download | ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.tar.gz ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.tar.bz2 ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.zip | |
synth: put direction into port desc
Diffstat (limited to 'src/synth/netlists.adb')
| -rw-r--r-- | src/synth/netlists.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb index 3de0a69fb..c62604929 100644 --- a/src/synth/netlists.adb +++ b/src/synth/netlists.adb @@ -159,7 +159,7 @@ package body Netlists is Ports_Desc := Port_Desc_Table.Last + 1; for I in 1 .. Nbr_Inputs + Nbr_Outputs loop Port_Desc_Table.Append - ((Name => No_Sname, Is_Inout => False, W => 0)); + ((Name => No_Sname, Dir => Port_In, W => 0)); end loop; Modules_Table.Append @@ -1575,7 +1575,7 @@ begin pragma Assert (Inputs_Table.Last = No_Input); Port_Desc_Table.Append ((Name => No_Sname, - Is_Inout => False, + Dir => Port_In, W => 0)); pragma Assert (Port_Desc_Table.Last = No_Port_Desc_Idx); |