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authorTristan Gingold <tgingold@free.fr>2019-09-11 06:29:18 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-11 06:37:28 +0200
commit0e5e045b01b6425ae3551ad1c463d8f8f57907d7 (patch)
treeee62774425173e2bbbe0fdc05222f0afece69084 /src/synth/synth-disp_vhdl.adb
parent99344d16bac958ce9abbeaa78f5efd82c7ea612a (diff)
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synth: improve support of negative integer values.
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
-rw-r--r--src/synth/synth-disp_vhdl.adb7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb
index 61bf31534..13d69c984 100644
--- a/src/synth/synth-disp_vhdl.adb
+++ b/src/synth/synth-disp_vhdl.adb
@@ -222,7 +222,12 @@ package body Synth.Disp_Vhdl is
when Iir_Kind_Integer_Type_Definition =>
-- FIXME: signed or unsigned ?
W := Typ.W;
- Put (" " & Pfx & " <= to_integer (unsigned");
+ Put (" " & Pfx & " <= to_integer (");
+ if Typ.Drange.Is_Signed then
+ Put ("signed");
+ else
+ Put ("unsigned");
+ end if;
if W = 1 then
Put ("'(0 => ");
else