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| author | Tristan Gingold <tgingold@free.fr> | 2023-02-08 11:31:04 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:04:34 +0100 |
| commit | 99dbf1376808a1bffb6886811d1585e34673b078 (patch) | |
| tree | ea7b786be0ec52ac6c9501aaa813317ff60470af /src/synth/synth-vhdl_eval.adb | |
| parent | 410f08aa700ee3c4cee834de2266ee9a09fd27bf (diff) | |
| download | ghdl-99dbf1376808a1bffb6886811d1585e34673b078.tar.gz ghdl-99dbf1376808a1bffb6886811d1585e34673b078.tar.bz2 ghdl-99dbf1376808a1bffb6886811d1585e34673b078.zip | |
synth: use same layout for records in memory as translate
Diffstat (limited to 'src/synth/synth-vhdl_eval.adb')
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index ec3b19e99..23bb3dac8 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -751,7 +751,7 @@ package body Synth.Vhdl_Eval is begin Bnd := (Dir => Dir_To, Left => 1, Right => Int32 (Len), Len => Uns32 (Len)); - Typ := Create_Array_Type (Bnd, True, Styp.Uarr_El); + Typ := Create_Array_Type (Bnd, True, True, Styp.Uarr_El); Res := Create_Memory (Typ); for I in Str'Range loop |