diff options
author | Tristan Gingold <tgingold@free.fr> | 2022-06-04 08:47:37 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2022-06-04 16:27:47 +0200 |
commit | b36bdd7e0dc9988cd930631419c4ea53898ed7fd (patch) | |
tree | eab7f353a40e5a5e3d59bcdf9e1eef5020721142 /src/synth/synth-vhdl_eval.adb | |
parent | 90ae71139bc39dc158f54e0337ed73f15033e77f (diff) | |
download | ghdl-b36bdd7e0dc9988cd930631419c4ea53898ed7fd.tar.gz ghdl-b36bdd7e0dc9988cd930631419c4ea53898ed7fd.tar.bz2 ghdl-b36bdd7e0dc9988cd930631419c4ea53898ed7fd.zip |
synth-vhdl_eval: add support for more operators.
Fix some corner cases
Diffstat (limited to 'src/synth/synth-vhdl_eval.adb')
-rw-r--r-- | src/synth/synth-vhdl_eval.adb | 74 |
1 files changed, 59 insertions, 15 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 5baced201..b14656b9e 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -848,39 +848,47 @@ package body Synth.Vhdl_Eval is Res := Compare_Uns_Uns (Left, Right, Greater, Expr) = Equal; return Create_Memory_Boolean (Res); end; - when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Uns => + when Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Sgn => declare Res : Boolean; begin - Res := Compare_Uns_Uns (Left, Right, Greater, Expr) /= Equal; + Res := Compare_Sgn_Sgn (Left, Right, Greater, Expr) = Equal; return Create_Memory_Boolean (Res); end; - when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat => declare Res : Boolean; begin - Res := Compare_Uns_Nat (Left, Right, Greater, Expr) /= Equal; + Res := Compare_Uns_Nat (Left, Right, Greater, Expr) = Equal; return Create_Memory_Boolean (Res); end; - when Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Sgn => + when Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Int => declare Res : Boolean; begin - Res := Compare_Sgn_Sgn (Left, Right, Greater, Expr) = Equal; + Res := Compare_Sgn_Int (Left, Right, Greater, Expr) = Equal; return Create_Memory_Boolean (Res); end; - when Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Eq_Int_Sgn => declare Res : Boolean; begin - Res := Compare_Uns_Nat (Left, Right, Greater, Expr) = Equal; + Res := Compare_Sgn_Int (Right, Left, Greater, Expr) = Equal; return Create_Memory_Boolean (Res); end; - when Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Int => + + when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Uns => declare Res : Boolean; begin - Res := Compare_Sgn_Int (Left, Right, Greater, Expr) = Equal; + Res := Compare_Uns_Uns (Left, Right, Greater, Expr) /= Equal; + return Create_Memory_Boolean (Res); + end; + when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Nat => + declare + Res : Boolean; + begin + Res := Compare_Uns_Nat (Left, Right, Greater, Expr) /= Equal; return Create_Memory_Boolean (Res); end; @@ -912,6 +920,20 @@ package body Synth.Vhdl_Eval is Res := Compare_Uns_Nat (Left, Right, Less, Expr) = Greater; return Create_Memory_Boolean (Res); end; + when Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Int => + declare + Res : Boolean; + begin + Res := Compare_Sgn_Int (Left, Right, Less, Expr) = Greater; + return Create_Memory_Boolean (Res); + end; + when Iir_Predefined_Ieee_Numeric_Std_Gt_Int_Sgn => + declare + Res : Boolean; + begin + Res := Compare_Sgn_Int (Right, Left, Greater, Expr) < Equal; + return Create_Memory_Boolean (Res); + end; when Iir_Predefined_Ieee_Numeric_Std_Ge_Uns_Uns => declare @@ -1027,6 +1049,20 @@ package body Synth.Vhdl_Eval is Res := Compare_Sgn_Sgn (Left, Right, Greater, Expr) < Equal; return Create_Memory_Boolean (Res); end; + when Iir_Predefined_Ieee_Numeric_Std_Lt_Int_Sgn => + declare + Res : Boolean; + begin + Res := Compare_Sgn_Int (Right, Left, Less, Expr) > Equal; + return Create_Memory_Boolean (Res); + end; + when Iir_Predefined_Ieee_Numeric_Std_Lt_Sgn_Int => + declare + Res : Boolean; + begin + Res := Compare_Sgn_Int (Left, Right, Greater, Expr) < Equal; + return Create_Memory_Boolean (Res); + end; when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log @@ -1035,24 +1071,32 @@ package body Synth.Vhdl_Eval is | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv => return Add_Uns_Uns (Left, Right, Expr); - when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int => - return Add_Sgn_Int (Left, Read_Discrete (Right), Expr); - when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int => return Add_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), Expr); + when Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns => + return Add_Uns_Nat (Right, To_Uns64 (Read_Discrete (Left)), Expr); + when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn => return Add_Sgn_Sgn (Left, Right, Expr); + when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int => + return Add_Sgn_Int (Left, Read_Discrete (Right), Expr); + when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn => + return Add_Sgn_Int (Right, Read_Discrete (Left), Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => return Sub_Uns_Uns (Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => return Sub_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns => + return Sub_Nat_Uns (To_Uns64 (Read_Discrete (Left)), Right, Expr); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int => - return Sub_Sgn_Int (Left, Read_Discrete (Right), Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn => return Sub_Sgn_Sgn (Left, Right, Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int => + return Sub_Sgn_Int (Left, Read_Discrete (Right), Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn => + return Sub_Int_Sgn (Read_Discrete (Left), Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns => return Mul_Uns_Uns (Left, Right, Expr); |