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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-18 08:57:27 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-18 08:57:27 +0200 |
| commit | f0900d17ff6ac00d3653e7aea5af166b603b155a (patch) | |
| tree | b7631cf8c8115cf8d1151f5c714c25a785c46efd /src/synth/synth-vhdl_stmts.adb | |
| parent | 712c08710de22ecbcbf42527ef516160591a1000 (diff) | |
| download | ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.tar.gz ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.tar.bz2 ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.zip | |
synth-vhdl_stmts: minor renaming
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index b0726d03b..ffa780625 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -2137,16 +2137,16 @@ package body Synth.Vhdl_Stmts is end loop; end Synth_Subprogram_Associations; - procedure Synth_Subprogram_Association (Subprg_Inst : Synth_Instance_Acc; - Caller_Inst : Synth_Instance_Acc; - Inter_Chain : Node; - Assoc_Chain : Node) + procedure Synth_Subprogram_Associations (Subprg_Inst : Synth_Instance_Acc; + Caller_Inst : Synth_Instance_Acc; + Inter_Chain : Node; + Assoc_Chain : Node) is Init : Association_Iterator_Init; begin Init := Association_Iterator_Build (Inter_Chain, Assoc_Chain); Synth_Subprogram_Associations (Subprg_Inst, Caller_Inst, Init); - end Synth_Subprogram_Association; + end Synth_Subprogram_Associations; -- Create wires for out and inout interface variables. procedure Synth_Subprogram_Association_Wires |