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authorTristan Gingold <tgingold@free.fr>2019-08-07 05:59:50 +0200
committerTristan Gingold <tgingold@free.fr>2019-08-08 04:33:32 +0200
commit97d3a89195c8aeb981a7f4171b939c48ec4bdfaa (patch)
treed7f4c9d6124a0a408be5d1e1003f44e33e14b5eb /src/vhdl/simulate/simul-simulation-main.adb
parent4e3f3f744ede1b4d6ad419383015dd6c78be1009 (diff)
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vhdl: remove severity from cover, report and severity from assume.
Diffstat (limited to 'src/vhdl/simulate/simul-simulation-main.adb')
-rw-r--r--src/vhdl/simulate/simul-simulation-main.adb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index d6c6ba0ff..ae768b3d0 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -477,7 +477,7 @@ package body Simul.Simulation.Main is
S_Num := Get_State_Label (S);
pragma Assert (S_Num = Get_PSL_Nbr_States (E.Stmt) - 1);
case Get_Kind (E.Stmt) is
- when Iir_Kind_Psl_Assume_Directive =>
+ when Iir_Kind_Psl_Assert_Directive =>
if Nvec (S_Num) then
Execute_Failed_Assertion
(E.Instance, "psl assertion", E.Stmt,