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author | Tristan Gingold <tgingold@free.fr> | 2022-09-19 07:27:42 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-09-19 07:27:42 +0200 |
commit | 8d3dcfb5bf4feffd59eaf2802b824059b3d75070 (patch) | |
tree | f7a03711e2dc7abd6ad24a9a9e9e129ea1d3e085 /src/vhdl/vhdl-annotations.adb | |
parent | f0900d17ff6ac00d3653e7aea5af166b603b155a (diff) | |
download | ghdl-8d3dcfb5bf4feffd59eaf2802b824059b3d75070.tar.gz ghdl-8d3dcfb5bf4feffd59eaf2802b824059b3d75070.tar.bz2 ghdl-8d3dcfb5bf4feffd59eaf2802b824059b3d75070.zip |
synth: rework subprogram associations (WIP)
Diffstat (limited to 'src/vhdl/vhdl-annotations.adb')
-rw-r--r-- | src/vhdl/vhdl-annotations.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 6957ba4e3..194341730 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -885,7 +885,9 @@ package body Vhdl.Annotations is Assoc_Inter := Inter_Chain; while Assoc /= Null_Iir loop Inter := Get_Association_Interface (Assoc, Assoc_Inter); - if Is_Copyback_Parameter (Inter) then + if Get_Kind (Assoc) /= Iir_Kind_Association_Element_By_Individual + and then Is_Copyback_Parameter (Inter) + then Create_Object_Info (Block_Info, Assoc, Kind_Object); end if; Next_Association_Interface (Assoc, Assoc_Inter); |