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authorTristan Gingold <tgingold@free.fr>2016-06-16 21:14:42 +0200
committerTristan Gingold <tgingold@free.fr>2016-06-17 20:21:41 +0200
commite2587eb9137f627f4ec51a80dfe641394197d975 (patch)
tree71977442e6eebccea7f351c738d752bf46cede4d /testsuite/gna/bug045/repro.vhdl
parent9f5bd757977aeb0f90466decc3b27f159ca612a4 (diff)
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Add a test for vcd and fst dumps.
Diffstat (limited to 'testsuite/gna/bug045/repro.vhdl')
-rw-r--r--testsuite/gna/bug045/repro.vhdl41
1 files changed, 41 insertions, 0 deletions
diff --git a/testsuite/gna/bug045/repro.vhdl b/testsuite/gna/bug045/repro.vhdl
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+entity sub is
+ generic (l : natural);
+ port (a : out bit;
+ b : bit_vector (0 to 3);
+ c : bit_vector (0 to l - 1));
+end sub;
+
+architecture behav of sub is
+begin
+ a <= b (0) xor c (0);
+end behav;
+
+entity tb is
+end tb;
+
+architecture behav of tb is
+ signal a : bit;
+ signal b: bit_vector (0 to 3);
+ signal c: bit_vector (0 to 7);
+
+ type state is (S0, S1, S_done);
+ signal s : state := S0;
+begin
+ my_sub: entity work.sub
+ generic map (l => c'length)
+ port map (a => a, b => b, c => c);
+
+ process
+ begin
+ wait for 1 ns;
+ assert a = '0';
+ b <= x"0";
+ c <= x"80";
+ s <= s1;
+ wait for 1 ns;
+ assert a = '1';
+ s <= S_done;
+ wait for 1 ns;
+ wait;
+ end process;
+end behav;