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author | Tristan Gingold <tgingold@free.fr> | 2018-11-16 21:00:12 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-11-16 21:00:12 +0100 |
commit | 342971aa2920aa01a1b636e892ef709e6abfdd37 (patch) | |
tree | f322c6db85cc9fe8f08ee9bf9c5862011ffb005d /testsuite/gna/bug090/crash10.vhdl | |
parent | ad252b4268f855b7df53092826b6f6a57ce4c4e3 (diff) | |
download | ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.tar.gz ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.tar.bz2 ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.zip |
Add bug090.
Diffstat (limited to 'testsuite/gna/bug090/crash10.vhdl')
-rw-r--r-- | testsuite/gna/bug090/crash10.vhdl | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/testsuite/gna/bug090/crash10.vhdl b/testsuite/gna/bug090/crash10.vhdl new file mode 100644 index 000000000..97f46b6de --- /dev/null +++ b/testsuite/gna/bug090/crash10.vhdl @@ -0,0 +1,62 @@ +library ieee; +use ieee.s_1164.all; + +entity clkgen is + generic (period : time := 10 ns); + port (signal clk : out std_logic := '0'); +end clkgen; + +architecture behav of clkgen is +begin + process + begin + clk <= not clk; + wait for period / 2; + end process; +end behav; + +entity hello is +end hello; + +architecture behav of hello is + signal clk : std_logic; + signal rst_n : std_logic; + signal din, dout, dout2 : std_logic_vector (7 downto 0); + + component clkgen is + generic (period : time := 10 ns); + port (signal clk : out std_logic); + end component; +begin + cclk : clkgen + generic map (period => 20 ns) + port map (clk => clk); + + rst_n <= '0' after 0 ns, '1' after 4 ns; + + p: process (clk) + begin + if rising_edge (clk) then + if rst_n then +q <= (others => '0'); + else q <= d; + end if; + end if; + end process p; + + process + variable v : natural := 0; + begin + wait until rst_n = '1'; + wait until clk = '0'; + + report 2start of tb" severity note; + + for i in 0 to 10 loop + case i is +when 0 | 3 => + for i,in din'range loop + din(i) <= '0'; + end loop; + when 1 => din <= b"00110011"; + when 2 =>ehav; |