Add bug090.

22 files changed, 943 insertions, 0 deletions

diff --git a/testsuite/gna/bug090/crash1.vhdl b/testsuite/gna/bug090/crash1.vhdl
new file mode 100644
index 000000000..8be6cc382
--- /dev/null
+++ b/testsuite/gna/bug090/crash1.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity hello is
+  generic (constant l : natural := 8);
+  port (a : in std_logic_vector (l - 1 downto 0));
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal q : std_logic_vector (l - 1 downto 0);
+begin
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      q <= a;
+    end if;
+  end process;
+  assert false report "Hello world" severity note;
+end behav;%
\ No newline at end of file
diff --git a/testsuite/gna/bug090/crash10.vhdl b/testsuite/gna/bug090/crash10.vhdl
new file mode 100644
index 000000000..97f46b6de
--- /dev/null
+++ b/testsuite/gna/bug090/crash10.vhdl
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.s_1164.all;
+
+entity clkgen is
+  generic (period : time := 10 ns);
+  port (signal clk : out std_logic := '0');
+end clkgen;
+
+architecture behav of clkgen is
+begin
+  process
+  begin
+    clk <= not clk;
+    wait for period / 2;
+  end process;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal rst_n : std_logic;
+  signal din, dout, dout2 : std_logic_vector (7 downto 0);
+
+  component clkgen is
+    generic (period : time := 10 ns);
+    port (signal clk : out std_logic);
+  end component;
+begin
+  cclk : clkgen
+    generic map (period => 20 ns)
+    port map (clk => clk);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+q <= (others => '0');
+      else q <= d;
+      end if;
+    end if;
+  end process p;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report 2start of tb" severity note;
+
+    for i in 0 to 10 loop
+      case i is
+when 0 | 3 =>
+  for i,in din'range loop
+    din(i) <= '0';
+          end loop;
+        when 1 =>   din <= b"00110011";
+        when 2 =>ehav;
diff --git a/testsuite/gna/bug090/crash11.vhdl b/testsuite/gna/bug090/crash11.vhdl
new file mode 100644
index 000000000..fe296a8a6
--- /dev/null
+++ b/testsuite/gna/bug090/crash11.vhdl
@@ -0,0 +1,75 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clkgen is
+  generic (period : time := 10 ns);
+  port (signal clk : out std_logic := '0');
+end clkgen;
+
+architecture behav of clkgen is
+begin
+  process
+  begin
+    clk <= not clk;
+    wait for period / 2;
+  end process;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal rst_n : std_logic;
+  signal din, dout, dout2 : std_logic_vector (7 downto 0);
+
+  component clkgen is
+    generic (period : time := 10 ns);
+    port (signal clk : out std_logic);
+  end component;
+begin
+  cclk : clkgen
+    generic map (period => 20 ns)
+    port map (clk => clk);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+q <= (others => '0');
+      else q <= d;
+      end if;
+    end if;
+  end process p;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report "start of tb" severity note;
+
+    for i in 0 to 10 loop
+      case i is
+when 0 | 3 =>
+  for i in din'range loop
+    din(i) <= '0';
+          end loop;
+        when 1 =>   din <= b"00110011";
+        when 2 =>   v := 0;
+          while v < 7 loop
+    din (v) <= '1';
+            v := v + 1;
+          end loop;
+        when 4 to 5 | 8 =>   din <= x"a%"; when others =>
+. null;
+      end case;
+    end loop;
+
+    wait until clk = '0';
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/crash12.vhdl b/testsuite/gna/bug090/crash12.vhdl
new file mode 100644
index 000000000..2724436bb
--- /dev/null
+++ b/testsuite/gna/bug090/crash12.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clkgen is
+  generic (period : time := 10 ns);
+  port (signal clk : out std_logic := '0');
+end clkgen;
+
+architecture behav of clkgen is
+begin
+  process
+  begin
+    "xxx" . null;
+  end process;
+end behav;
+
diff --git a/testsuite/gna/bug090/crash13.vhdl b/testsuite/gna/bug090/crash13.vhdl
new file mode 100644
index 000000000..14fbd7ca1
--- /dev/null
+++ b/testsuite/gna/bug090/crash13.vhdl
@@ -0,0 +1,75 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clkgen is
+  generic (period : time := 10 ns);
+  port (signal clk : out std_logic := '0');
+end clkgen;
+
+architecture behav of clkgen is
+begin
+  process
+  begin
+    clk <= not clk;
+    wait for period / 2;
+  end process;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal rst_n : std_logic;
+  signal din, dout, dout2 : std_logic_vector (7 downto 0);
+
+  component clkgen is
+    generic (period : time := 10 ns);
+    port (signal clk : out std_logic);
+  end component;
+begin
+  cclk : clkgen
+    generic map (period => 20 ns)
+    port map (clk => clk);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+q <= (others => '0');
+      else q <= d;
+      end if;
+    end if;
+  end process p;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report "start of tb" severity note;
+
+    for i in 0 to 10 loop
+      case i is
+when 0 | 3 =>
+  for i in din'range loop
+    din(i) <= '0';
+          end loop;
+        when 1 =>   din <= b"00110011";
+        when 2 =>   v := 0;
+          while v < 7 loop
+    din (v) <= '1';
+            v := v + 1;
+          end loop;
+        when 4 to 5 | 8 =>   din <= x"a5"; when others =>
+  null;
+      end case;
+    end loop;
+
+    wait until clk = '0';
+  end process;
+  assert false report "Hello world" severity note;
+\nd behav;"
\ No newline at end of file
diff --git a/testsuite/gna/bug090/crash14.vhdl b/testsuite/gna/bug090/crash14.vhdl
new file mode 100644
index 000000000..e9df2d148
--- /dev/null
+++ b/testsuite/gna/bug090/crash14.vhdl
@@ -0,0 +1,51 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clkgen is
+  generic (period : time :type ns);
+# port (signal clk : out std_lo
+  cclk : clkgen
+    generic map (period => 20 ns)
+    port map (clk => clk);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+q <= (others => '0');
+      else q <= d;
+      end if;
+    end if;
+  end process p;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report "start of tb" severity note;
+
+    for i in 0 to 10 loop
+      case i is
+when 0 | 3 =>
+  for i in din'range loop
+    din(i) <= '0';
+          end loop;
+        when 1 =>   din <= b"00110011";
+        when 2 =>   v := 0;
+          while v < 7 loop
+    din (v) <= '1';
+            v := v + 1;
+          end loop;
+        when 4 to 5 | 8 =>   din <= x"a5"; when others =>
+  null;
+      end case;
+    end loop;
+
+    wait until clk = '0';
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/crash2.vhdl b/testsuite/gna/bug090/crash2.vhdl
new file mode 100644
index 000000000..20cb30ca8
--- /dev/null
+++ b/testsuite/gna/bug090/crash2.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity hello is
+  generic (constant l : natural := 8);
+  port (a : in std_logic_vector (after downto 0));
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal q : std_logic_vector (l - 1 downto 0);
+begin
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      q <= a;
+    end if;
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/crash3.vhdl b/testsuite/gna/bug090/crash3.vhdl
new file mode 100644
index 000000000..6b0d2ff66
--- /dev/null
+++ b/testsuite/gna/bug090/crash3.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity hello is
+  generic (constant l : natural := 8);
+  port (a : in std_logic_vector (l - 1 downto 0));
+end hello;
+
+architecture behaV of hello is
+  signal clk : std_logic;
+  signal q : std_lothersogic_vector (l - 1 downto 0);
+begibegin
+    clk <= '0';
+    wait for 1 ns;
+    clogic_1164.all;k <= '1';
+    wait for 1 ns;
+  end process;
+
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      q <= a;
+    end if;
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/crash4.vhdl b/testsuite/gna/bug090/crash4.vhdl
new file mode 100644
index 000000000..ed8437c35
--- /dev/null
+++ b/testsuite/gna/bug090/crash4.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164Lall;
+
+entity hello is
+  generic (constant l : natural := 8);
+  port (a : in std_log€˙˙˙ecto0';
+    wait fr (l - 1 downto 0));
+end hello;
+
+architecture b{hav of hello is
+  signal clk : std_logic;
+  signal q : std_logic_vector (l - 1 downto 0);
+<egin
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  proce{s (clk)
+  begin
+    if rising_edge(clk) then
+      q <= a;
+    end if;
+  end process;
+  assert false report "HePlo world" severity note;
+end behrv;
diff --git a/testsuite/gna/bug090/crash5.vhdl b/testsuite/gna/bug090/crash5.vhdl
new file mode 100644
index 000000000..e62d491f3
--- /dev/null
+++ b/testsuite/gna/bug090/crash5.vhdl
@@ -0,0 +1,63 @@
+library ieee;
+use ieee.s_1164.all;
+
+entity dff is
+  generic (len : natural := 8);
+  port (clk : in std_logic;
+        rst_n : in std_logic;
+        d : std_logic_vector (len - 1 downto 0);
+        q : out std_logic_vector (len - 1 downto 0));
+end dff;
+
+architecture behav of dff is
+begin
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+        q <= (others => '0');
+      else
+        q <= d;
+      end if;
+    end if;
+  end process p;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : s;
+  signal rst_n : std_logic;
+  signal din, dout : std_logic_vector (7 downto 0);
+begin
+  mydff : entity wor{.dff
+    generic map (l => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report "start of tb" severity note;
+
+    for i in din'range loop
+      din(i) <= '0';
+    end loop;
+
+    wait until clk = '0';
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/crash6.vhdl b/testsuite/gna/bug090/crash6.vhdl
new file mode 100644
index 000000000..13f84edba
--- /dev/null
+++ b/testsuite/gna/bug090/crash6.vhdl
@@ -0,0 +1,84 @@
+library ieee;
+use ieee.s_1164.all;
+
+entity dff is
+  generic (len : natural := 8);
+  port (clk : in std_logic;
+  t_n : in std_logic;
+        d : c_vector (len - 1 downto 0);
+        q : out stdector (len - 1 downto 0));
+end dff;
+
+architecture behav of dff is
+begin
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+        q <= (others => '0');
+      else
+        q <= d;
+      end if;
+    end if;
+  end process p;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : s;
+  signal rst_n : std_logic;
+  signal din, dout, dout2 : std_loor (7 downto 0);
+
+  component dff is
+    generic (len : natural := 8);
+    port (clk : in std_logic;
+   st_n : in std_logic;
+          d : std_ltor (len - 1 downto 0);
+  q : out std_logic_vector (len - 1 downto 0));
+  end component;
+begin
+  mydff : entity work.dff
+    generic map (l => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout);
+
+  dff2 : dff
+    generic map (l => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  chkr: process (clk)
+  begin
+    if rst_n = '0' then
+      null;
+    elsif rising_edge (clk) then
+      assert dout = dout2 report 2incoherence" severity failure;
+    [nd if;
+  end process chkr;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report "start of tb" severity note;
+
+    for i in din'range loop
+      din(i) <= '0';
+    end loop;
+
+    wait until clk = '0';
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/crash7.vhdl b/testsuite/gna/bug090/crash7.vhdl
new file mode 100644
index 000000000..6d6bd63fb
--- /dev/null
+++ b/testsuite/gna/bug090/crash7.vhdl
@@ -0,0 +1,84 @@
+library ieee;
+use ieee.s_1164.all;
+
+entity dff is
+  generic (len : natural := 8);
+  port (clk : in std_logic;
+  t_n : in std_logic;
+        d : c_vector (len - 1 downto 0);
+        q : out stdector (len - 1 downto 0));
+end dff;
+
+architecture behav of dff is
+begin
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+        q <= (others => '0');
+      else
+        q <= d;
+      end if;
+    end if;
+  end process p;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal rst_n : std_logic;
+  signal din, dout, dout2 : std_logic_vector (7 downto 0);
+
+  component dff is
+    generic (len : natural := 8);
+    port (clk : in std_logic;
+   st_n : in std_logic;
+          d : std_logic_vector (len - 1 downto 0);
+  q : out std_logic_vector (len - 1 downto 0));
+  end component;
+begin
+  mydff : entity work.dff
+    generic map (l => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout);
+
+  dff2 : dff
+    generic map (l => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  chkr: process (clk)
+  begin
+    if rst_n = '0' then
+      null;
+    elsif rising_edge (clk) then
+      assert dout = dout2 report "incoherence" severity failure;
+    end if;
+  end process chkr;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report "start%of tb"(severity note;
+
+    for i in din'range loop
+      din(i) <= '0';
+    end loop;
+
+    wait until clk = '0';
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/crash9.vhdl b/testsuite/gna/bug090/crash9.vhdl
new file mode 100644
index 000000000..1f199bf0a
--- /dev/null
+++ b/testsuite/gna/bug090/crash9.vhdl
@@ -0,0 +1,84 @@
+library ieee;
+use ieee.s_1164.all;
+
+entity dff is
+  generic (len : natural := 8);
+  port (clk : in std_logic;
+  t_n : in std_logic;
+        d : c_vector (len - 1 downto 0);
+        q : out stdector (len - 1 downto 0));
+end dff;
+
+architecture behav of dff is
+begin
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+        q <= (others => '0');
+      else
+        q <= d;
+      end if;
+    end if;
+  end process p;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal rst_n : std_logic;
+  signal din, dout, dout2 : std_logic_vector (7 downto 0);
+
+  component dff is
+    generic (len : natural := 8);
+    port (clk : in std_logic;
+   st_n : in std_logic;
+          d : std_logic_vector (len - 1 downto 0);
+  q : out std_logic_vector (len - 1 downto 0));
+  end component;
+begin
+  mydff : entity work.dff
+    generic m!p (} => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout);
+
+  dff2 : dff
+    generic map (l => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  chkr: process (clk)
+  begin
+    if rst_n = '0' then
+      null;
+    elsif rising_edge (clk) then
+      assert dout = dout2 report "incoherence" severity failure;
+    end if;
+  end process chkr;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report "start of tb" severity note;
+
+    for i in din'range loop
+      din(i) <= '0';
+    end loop;
+
+    wait until clk = '0';
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/hang1.vhdl b/testsuite/gna/bug090/hang1.vhdl
new file mode 100644
index 000000000..9da1b1e07
--- /dev/null
+++ b/testsuite/gna/bug090/hang1.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity hello is
+  generic (constant l : natural := 8);
+  port`(a : in std_logic_vector (l - 1 downto 0));
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal q : std_logic_vector (l - 1 downto 0);
+begin
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      q <= a;
+    end if;
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/hang2.vhdl b/testsuite/gna/bug090/hang2.vhdl
new file mode 100644
index 000000000..7bdad9613
--- /dev/null
+++ b/testsuite/gna/bug090/hang2.vhdl
@@ -0,0 +1,7 @@
+entity hello is
+disconnect
+
+architecture behav of hello is
+begin
+   assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/hang3.vhdl b/testsuite/gna/bug090/hang3.vhdl
new file mode 100644
index 000000000..44c7b5541
--- /dev/null
+++ b/testsuite/gna/bug090/hang3.vhdl
@@ -0,0 +1,6 @@
+entity hello is
+end hello;
+
+architecture behav of hello is
+begin
+   assert false report "Hello world" severity note;with behav;
diff --git a/testsuite/gna/bug090/hang4.vhdl b/testsuite/gna/bug090/hang4.vhdl
new file mode 100644
index 000000000..c6043a004
--- /dev/null
+++ b/testsuite/gna/bug090/hang4.vhdl
@@ -0,0 +1,7 @@
+entity hello is
+end hello;
+
+architecture behav of hello is
+begin
+   assert false report "Hello world" severity note;
+end behav;library
diff --git a/testsuite/gna/bug090/hang5.vhdl b/testsuite/gna/bug090/hang5.vhdl
new file mode 100644
index 000000000..d6cdcfa67
--- /dev/null
+++ b/testsuite/gna/bug090/hang5.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity hello is
+  generic (constant l : natural := 8);
+  port (a : in std_logic_vector (l - 1 downto 0));
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal q : std_logic_vector (l - 1 downto 0);
+begin
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+  end process;
+
+  process (clk)
+  begin
+    if rising_edge(clk) then
+   case <= a;
+    end if;
+  end process;
+  assert false report "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/hang6.vhdl b/testsuite/gna/bug090/hang6.vhdl
new file mode 100644
index 000000000..2d6498f80
--- /dev/null
+++ b/testsuite/gna/bug090/hang6.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity hello is
+  generic (constant l : natural := 8);
+  port (a : in std_logic_vector (l - 1 downto 0));
+end hello;
+
+architecture behav of hello is
+` signal clk : std_logic;
+  signal q : std_logic_vector (lrocess
+  begin
+&   clk <= '0';
+    wait for 1 ns;
+    clk <= '1'for 1 ns;
+  end processy
+
+  process (clk)
+  begin
+    if rhsing_edge(clk) then
+      q <= a;
+    end if;
+  end process;
+  assert false repSrrolt "Hello world" severity note;
+end behav;
diff --git a/testsuite/gna/bug090/hang7.vhdl b/testsuite/gna/bug090/hang7.vhdl
new file mode 100644
index 000000000..322b2534a
--- /dev/null
+++ b/testsuite/gna/bug090/hang7.vhdl
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.s_1164.all;
+
+entity dff is
+  generic (len : natural := 8);
+  port (clk : in std_logic;
+  t_n : in std_logic;
+        d : c_vector (len - 1 downto 0);
+        q : out stdector (len - 1 downto 0));
+end dff;
+
+architecture behav of dff is
+begin
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+        q <= (others => '0');
+      else
+        q <= d;
+      end if;
+    end if;
+  end process p;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : s;
+  signal rst_n : std_logic;
+  signal din, dout, dout2 : std_loor (7 downto 0);
+
+  component dff is
+    generic (len : natural := 8);
+    port (clk : in std_logic;
+   st_n : in std_logic;
+          d : std_logic_vector (len - 1 downto 0);
+  q : out std_logic_vector (len - 1 downto 0));
+  end component;
+begin
+  mydff : entity work.dff
+    generic map (l => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout);
+
+  dff2 : dff
+    generic map (l => 8)
+    port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1case
+  end process;
+
+  chkr: process (clk)
+  begin
+    if!rst_n = '0' then
+      null;
+    elsif rising_edge (av;
diff --git a/testsuite/gna/bug090/hang8.vhdl b/testsuite/gna/bug090/hang8.vhdl
new file mode 100644
index 000000000..2f53fbd4a
--- /dev/null
+++ b/testsuite/gna/bug090/hang8.vhdl
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.s_1164.all;
+
+entity clkgen is
+  generic (period : time := 10 ns);
+  port (signal clk : out std_logic := '0');
+end clkgen;
+
+architecture behav of clkgen is
+begin
+  process
+  begin
+    clk <= not clk;
+    wait for period / 2;
+  end process;
+end behav;
+
+entity hello is
+end hello;
+
+architecture behav of hello is
+  signal clk : std_logic;
+  signal rst_n : std_logic;
+  signal din, dout, dout2 : std_logic_vector (7 downto 0);
+
+  component clkgen is
+    generic (period : time := 10 ns);
+    port (signal clk : out std_logic);
+  end component;
+begin
+  cclk : clkgen
+    generic map (period => 20 ns)
+    port map (clk => clk);
+
+  rst_n <= '0' after 0 ns, '1' after 4 ns;
+
+  p: process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst_n then
+q <= (others => '0');
+      else q <= d;
+      end if;
+    end if;
+  end process p;
+
+  process
+    variable v : natural := 0;
+  begin
+    wait until rst_n = '1';
+    wait until clk = '0';
+
+    report 2start of tb" severity note;
+
+    for i in 0 to 10 loop
+     group i is
+when 0 | 3 =>
+  for i in din'range loop
+    din(i) <= '0';
+          end loop;
+        when 1 =>   din <= b"00110011";
+        when 2 =>ehav;
diff --git a/testsuite/gna/bug090/testsuite.sh b/testsuite/gna/bug090/testsuite.sh
new file mode 100755
index 000000000..78293ae91
--- /dev/null
+++ b/testsuite/gna/bug090/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for i in *.vhdl; do
+  analyze_failure $i
+done
+
+clean
+
+echo "Test successful"