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authorTristan Gingold <tgingold@free.fr>2016-12-05 03:21:33 +0100
committerTristan Gingold <tgingold@free.fr>2016-12-05 03:25:22 +0100
commit0f94031b6843794dfdd7e1c0a1b72235908cecd9 (patch)
tree648f5d784b5bc8bee05c2116866e8742d172192b /testsuite/gna/issue107
parentb7a72ac6b84fca5fdd84a0656b87ad25a643c1f0 (diff)
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Add testcase for #107
Diffstat (limited to 'testsuite/gna/issue107')
-rw-r--r--testsuite/gna/issue107/test1.vhdl28
-rw-r--r--testsuite/gna/issue107/testpkg.vhdl16
-rwxr-xr-xtestsuite/gna/issue107/testsuite.sh12
3 files changed, 56 insertions, 0 deletions
diff --git a/testsuite/gna/issue107/test1.vhdl b/testsuite/gna/issue107/test1.vhdl
new file mode 100644
index 000000000..4e3e74174
--- /dev/null
+++ b/testsuite/gna/issue107/test1.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+
+entity ApbMasterBfmE is
+ generic (
+ G_ADDR_WIDTH : positive := 8; --* address bus width
+ G_DATA_WIDTH : positive := 8; --* data bus width
+ G_SLAVE_COUNT : positive := 1
+ );
+ port (
+ PRreset_n_i : in std_logic;
+ PClk_i : in std_logic
+ );
+end entity ApbMasterBfmE;
+
+
+package MyTestPkg is new work.TestPkg generic map (G_TEST => 17);
+
+
+architecture sim of ApbMasterBfmE is
+
+ use work.MyTestPkg.all;
+
+begin
+
+ assert false report "done" severity note;
+
+end architecture sim;
diff --git a/testsuite/gna/issue107/testpkg.vhdl b/testsuite/gna/issue107/testpkg.vhdl
new file mode 100644
index 000000000..917b08976
--- /dev/null
+++ b/testsuite/gna/issue107/testpkg.vhdl
@@ -0,0 +1,16 @@
+package TestPkg is
+
+ generic (
+ G_TEST : positive := 8
+ );
+end package TestPkg;
+
+
+package body TestPkg is
+
+ procedure TestReport is
+ begin
+ report "G_TEST :" & to_string(G_TEST);
+ end procedure;
+
+end package body;
diff --git a/testsuite/gna/issue107/testsuite.sh b/testsuite/gna/issue107/testsuite.sh
new file mode 100755
index 000000000..4f35fc111
--- /dev/null
+++ b/testsuite/gna/issue107/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+analyze testpkg.vhdl
+analyze test1.vhdl
+
+clean
+
+echo "Test successful"