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authorTristan Gingold <tgingold@free.fr>2020-06-30 18:43:46 +0200
committerTristan Gingold <tgingold@free.fr>2020-06-30 19:34:52 +0200
commite854f72b1ef2b83ded3812d2b913c4c30aaef86b (patch)
tree2ebdff5a341ff9771ee61f94ab12be2e8ff4d090 /testsuite/gna/issue1384/tb_issue.vhdl
parent8ab2ac7308cde26aa3fd7e9c5caddc8f789911ef (diff)
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testsuite/gna: add a test for #1384
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-rw-r--r--testsuite/gna/issue1384/tb_issue.vhdl22
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diff --git a/testsuite/gna/issue1384/tb_issue.vhdl b/testsuite/gna/issue1384/tb_issue.vhdl
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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity tb_issue is
+end entity tb_issue;
+
+architecture dataflow of tb_issue is
+
+ type arec is record
+ member : std_logic_vector(31 downto 0);
+ end record arec;
+
+ signal a : arec;
+
+begin
+
+ process
+ begin
+ a.member <= (0 => '1', others => '0');
+ end process;
+
+end architecture dataflow;