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author | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:08:26 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:08:26 +0100 |
commit | 41b8812dad8f9c78fb7dd652843b7a8855b0fb92 (patch) | |
tree | 39281d8dc5b6525edf3f537ffaa403a175f2df35 /testsuite/gna/issue2346/aggr.vhdl | |
parent | d0129fb0e2e89128de8d8569a32cd8fb97fa0b8c (diff) | |
download | ghdl-41b8812dad8f9c78fb7dd652843b7a8855b0fb92.tar.gz ghdl-41b8812dad8f9c78fb7dd652843b7a8855b0fb92.tar.bz2 ghdl-41b8812dad8f9c78fb7dd652843b7a8855b0fb92.zip |
testsuite/gna: add a test for #2346
Diffstat (limited to 'testsuite/gna/issue2346/aggr.vhdl')
-rw-r--r-- | testsuite/gna/issue2346/aggr.vhdl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/gna/issue2346/aggr.vhdl b/testsuite/gna/issue2346/aggr.vhdl new file mode 100644 index 000000000..c9f0f0add --- /dev/null +++ b/testsuite/gna/issue2346/aggr.vhdl @@ -0,0 +1,32 @@ +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.numeric_std_unsigned.all ; + +entity AggregateWithDelay is +end AggregateWithDelay ; +architecture test of AggregateWithDelay is + constant tpd : time := 1 ns ; + signal Clk : std_logic := '0' ; + signal A1, A0 : std_logic ; +begin + + Clk <= not Clk after 5 ns ; + + DriveDataProc : process + variable A : std_logic_vector(1 downto 0) ; + begin + wait until Clk = '1'; + + for i in 7 downto 0 loop + (A1, A0) <= to_slv(i, 2) after tpd ; +-- The following is the work around +-- A := to_slv(i, 2) ; +-- A1 <= A(1) after tpd ; +-- A0 <= A(0) after tpd ; + wait until Clk = '1' ; + wait until Clk = '1' ; + end loop ; + std.env.stop ; + wait ; + end process ; +end; |